Intellectual property protection of IP cores through high-level watermarking

Abstract

In this paper a watermarking technique for Intellectual Property Protection (IPP) of FPGA-based systems is proposed. The aim is to protect the author rights of reusable IP cores by means of a digital signature that uniquely identifies both the original design and the design recipient. The proposed watermarking technique relies on a procedure that spreads the digital signature in cells of memory structures at Hardware Description Language (HDL) design level, not increasing the area of the system. This signature is preserved through synthesis, placement and routing processes. The technique includes a procedure for signature extraction requiring minimal modifications to the system. Thus, it is possible to detect the ownership rights without interfering the normal operation of the system and providing high invulnerability. To illustrate the properties of the proposed watermarking technique, both protected and unprotected design examples are compared in terms of area and performance. The analysis of the results shows that the area increase is very low while throughput penalization is almost negligible.

Design Time Optimization for Hardware Watermarking Protection of HDL Designs

“…IPP@HDL signature hosting strategy [ 17 ] protects digital systems by spreading the bits of a digital signature [ 28 ] through combinational logic included in the high-level description of the design [ 17 , 29 ]. The digital signature is propagated through the whole design flow down to the physical implementation, alleviating the requirement of additional system resources.…”

Intellectual property protection (IPP) using obfuscation in C, VHDL, and Verilog coding

“…Much consideration has been given on watermarking [6][7][8][9][10][11][12][13][14][15][16] and protection approaches in the past, see Fig. 1.…”