Inter-cluster communication models for clustered VLIW processors

Terechko, Andrei; Thénaff, Erwan Le; Garg, Manish; Eijndhoven, J. van; Corporaal, Henk

doi:10.1109/hpca.2003.1183552

Cited by 36 publications

(39 citation statements)

References 15 publications

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“…A lot of research for VLIW architectures focuses on Clustered VLIW [18], VLIW code compression [19] and Value prediction module [21] in order to get better performance. Using these skills, the performance of NP applications could be improved with smaller code size (by compression scheme) and more aggressive parallelism (by clustered architecture).…”

Section: Discussionmentioning

confidence: 99%

Exploiting Statically Identified ILP for Network Processor Applications

Lee¹

2010

IJCEE

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Abstract-Along with sharply increasing bandwidth requirements, modern network applications and new protocols demand highly intelligent and sophisticated processing over the network. Since these workloads require processing capability beyond state-of-the-art microprocessors, parallel architectures are required in order to handle the packet data without slowing down line speed. Network processors with various parallel architectures are appearing in the market, however, a thorough investigation of the implications of static versus dynamic scheduling of this class of emerging workloads has not been done. In this paper, we characterize the performance and power dissipation of statically identified ILP architectures, and we also compare them to dynamically scheduled architectures for network processing. In dynamically scheduled architectures, the power consumption of the instruction window greatly increases with increasing issue widths. On the other hand, statically scheduled architectures show better performance, as well as tremendous advantages in power, since they do not have instruction window wakeup/select, reorder buffer, and other scheduling related hardware modules. With the large parallelism and the loop nature of network applications, our experimental analysis supports static scheduling as an appropriate strategy for network processor applications.

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Section: Discussionmentioning

confidence: 99%

Exploiting Statically Identified ILP for Network Processor Applications

Lee¹

2010

IJCEE

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“…Each cluster has its own functional units and local register file. Clusters are connected by an inter-cluster communication network [2].…”

Section: Introductionmentioning

confidence: 99%

An efficient heuristic for instruction scheduling on clustered vliw processors

Zhang

Xue

2011

Proceedings of the 14th International Conference on Compilers, Architectures and Synthesis for Embedded Systems

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Clustering is a well-known technique for improving the scalability of classical VLIW processors. A clustered VLIW processor consists of multiple clusters, each of which has its own register file and functional units. This paper presents a novel phase coupled priority-based heuristic for scheduling a set of instructions in a basic block on a clustered VLIW processor. Our heuristic converts the instruction scheduling problem into the problem of scheduling a set of instructions with a common deadline. The priority of each instruction vi is the lmax(vi)-successor-tree-consistent deadline which is the upper bound on the latest completion time of vi in any feasible schedule for a relaxed problem where the precedence-latency constraints between vi and all its successors, as well as the resource constraints are considered. We have simulated our heuristic, UAS heuristic and Integrated heuristic on the 808 basic blocks taken from the MediaBench II benchmark suite using six processor models. On average, for the six processor models, our heuristic improves 25%, 25%, 33%, 23%, 26%, 27% over UAS heuristic, respectively, and 15%, 16%, 15%, 9%, 20%, 8% over Integrated heuristic, respectively.

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“…However, two published results on evaluation of various intercluster interconnect mechanisms in clustered VLIW processors [19] and [8] reported substantial performance gains in number of cycles when various other mechanisms are used. However, both these studies used few specific design points for evaluating bus based interconnects.…”

Section: Introductionmentioning

confidence: 99%

“…Clustering the VLIW architecture into a number of small sets of FUs, wherein each such set has its own RF is a natural solution to such a scalability problem. However, the inter-cluster interconnect in such architectures plays a crucial role in processor performance [19] and [8].…”

Section: Introductionmentioning

confidence: 99%