Interconnect delay minimization using a novel pre-mid-post buffer strategy

Prasad, V.; Desai, Madhav P.

doi:10.1109/icvd.2003.1183171

Cited by 9 publications

(11 citation statements)

References 12 publications

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“…The related structure is named as "Unequal buffer partitioning network" against "Equal buffer partitioning network" that was mentioned above. The optimum delay is a function of various parameters such as the buffers sizes, the interconnect segments lengths, the load and so on [9], [11], [12], [15]- [17], [19]- [22]. It is shown that for the optimization of a buffer inserted interconnect behavior, the energy-delay product minimization is better than the delay minimization.…”

Section: Repeater Insertion As a Technique For The Delay Reductionmentioning

confidence: 99%

“…The repeater (buffer) insertion technique is generally used to reduce the delay of long (semi global) and global interconnects [9], [11]- [16]. An analytical model for obtaining the optimal buffer size and segment length for an equal partitioning network, in which the buffers sizes and segments lengths are constant, has been presented [12], [14], [17].…”

Section: Repeater Insertion As a Technique For The Delay Reductionmentioning

confidence: 99%

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Interconnect Challenges and Carbon Nanotube as Interconnect in Nano VLSI Circuits

Fathi¹,

Forouzandeh²

2010

Carbon Nanotubes

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This chapter discusses about the behavior of Carbon Nanotube (CNT) different structures which can be used as interconnect in Very Large Scale (VLSI) circuits in nanoscale regime. Also interconnect challenges in VLSI circuits which lead to use CNT as interconnect instead of Cu, is reviewed. CNTs are classified into three main types including Single-walled Carbon Nanotube (SWCNT), CNT Bundle, and Multi-walled Carbon Nanotube (MWCNT). Because of extremely high quantum resistance of a SWCNT which is about 6.45 kΩ, rope or bundle of CNTs are used which consist of parallel CNTs in order to overcome the high delay time due to the high intrinsic (quantum) resistance. Also MWCNTs which consist of parallel shells, present much less delay time with respect to SWCNTs, for the application as interconnects. In this chapter, first a short discussion about interconnect challenges in VLSI circuits is presented. Then the repeater insertion technique for the delay reduction in the global interconnects will be studied. After that, the parameters and circuit model of a CNT will be discussed. Then a brief review about the different structures of CNT interconnects including CNT bundle and MWCNT will be presented. At the continuation, the time domain behavior of a CNT bundle interconnect in a driver-CNT bundle-load configuration will be discussed and analyzed. In this analysis, CNT bundle is modeled as a transmission line circuit model. At the end, a brief study of stability analysis in CNT interconnects will be presented. Interconnect Challenges in VLSI CircuitsAs interconnect feature sizes shrink, copper resistivity increases due to surface and grain boundary scatterings and also surface roughness [1]. Furthermore, wires, especially power and ground lines, are becoming more and more vulnerable to electromigration because of rapid increases in current densities [2]. The resistance of copper interconnects, with crosssectional dimensions of the order of the mean free path of electrons (~40 nm in Cu at room temperature) in current and imminent technologies [2], is increasing rapidly under the combined effects of enhanced grain boundary scattering, surface scattering and the presence of the highly resistive diffusion barrier layer [3]. The steep rise in parasitic resistance of copper interconnects poses serious challenges for interconnect delay [2]

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Section: Repeater Insertion As a Technique For The Delay Reductionmentioning

confidence: 99%

Section: Repeater Insertion As a Technique For The Delay Reductionmentioning

confidence: 99%

Interconnect Challenges and Carbon Nanotube as Interconnect in Nano VLSI Circuits

Fathi¹,

Forouzandeh²

2010

Carbon Nanotubes

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“…Therefore placement synthesis and mapping should be considered during synthesis and technology mapping. Once the cell positions are known, the model can be used to accurately predict the interconnect performance [19]. Fig.6 shows delay for three different wire line lengths.…”

Section: Amentioning

confidence: 99%

Interconnect sizing and spacing with consideration of buffer insertion for simultaneous crosstalk-delay optimization

Hasani

Masoumi

2008

2008 3rd International Conference on Design and Technology of Integrated Systems in Nanoscale Era

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As integrated circuits (ICs) are scaled into nanometre dimensions and operate in gigahertz frequencies, interconnects have become critical in determining system performance and reliability. In this paper we propose a new approach to investigate crosstalk reduction techniques which helps to have simultaneous optimization of interconnect delay and crosstalk noise in deep submicron VLSI circuits. The optimization problem is modelled by solving a new cost function to find a minimum cost for both crosstalk noise and delay which are conflicting in nature. Through MATLAB software, a system of three coupled wires is modelled as a RC distributed network. The results indicate the number of optimum available solutions including wire sizing, wire spacing and buffer insertion in which crosstalk reduction techniques can be useful for both crosstalk noise and delay.

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“…Also various methods have been proposed to reduce the power, which most of them have focused on the switch boxes as a part of interconnects and routing resources [14][15][16][17][18][19][20]. Buffer insertion is one of the most effective methods for improving interconnects' performance, directly reducing delay or reducing delay via reducing crosstalk effects [21][22][23][24][25][26][27]. Most of these methods are easily implemented in ASIC circuits, but it is too complicated to use them in FPGAs.…”

Section: Introductionmentioning

confidence: 99%

Reducing expected delay and power in FPGAs using buffer insertion in single-driver wires

Bagheri

Masoumi

2012

Microelectronics Journal

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Interconnect delay minimization using a novel pre-mid-post buffer strategy

Cited by 9 publications

References 12 publications

Interconnect Challenges and Carbon Nanotube as Interconnect in Nano VLSI Circuits

Interconnect Challenges and Carbon Nanotube as Interconnect in Nano VLSI Circuits

Interconnect sizing and spacing with consideration of buffer insertion for simultaneous crosstalk-delay optimization

Reducing expected delay and power in FPGAs using buffer insertion in single-driver wires

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