Interconnect sizing and spacing with consideration of buffer insertion for simultaneous crosstalk-delay optimization

Abstract

As integrated circuits (ICs) are scaled into nanometre dimensions and operate in gigahertz frequencies, interconnects have become critical in determining system performance and reliability. In this paper we propose a new approach to investigate crosstalk reduction techniques which helps to have simultaneous optimization of interconnect delay and crosstalk noise in deep submicron VLSI circuits. The optimization problem is modelled by solving a new cost function to find a minimum cost for both crosstalk noise and delay which are conflicting in nature. Through MATLAB software, a system of three coupled wires is modelled as a RC distributed network. The results indicate the number of optimum available solutions including wire sizing, wire spacing and buffer insertion in which crosstalk reduction techniques can be useful for both crosstalk noise and delay.

Reducing expected delay and power in FPGAs using buffer insertion in single-driver wires

“…Also various methods have been proposed to reduce the power, which most of them have focused on the switch boxes as a part of interconnects and routing resources [14][15][16][17][18][19][20]. Buffer insertion is one of the most effective methods for improving interconnects' performance, directly reducing delay or reducing delay via reducing crosstalk effects [21][22][23][24][25][26][27]. Most of these methods are easily implemented in ASIC circuits, but it is too complicated to use them in FPGAs.…”

Crosstalk in VLSI partially coupled interconnect structures, a comprehensive evaluation

“…Moreover, it causes the delay and power to increase, while the performance and reliability of circuits to decline. To reduce the crosstalk noise, different methods have been proposed including shielding method [5,7], repeater insertion [8][9][10], device sizing [11,12], various routing techniques [13][14][15] and input coding [16,17].…”

A novel low-swing interconnect optimization model with delay and bandwidth constraints

“…In order to meet performance requirements arising from increasing clock frequency and increasing complexity, many methods, such as optimal repeater insertion (ORI), [1,2] wire spacing and sizing, [3] lowswing circuit, [4,5] bus encoding, [6] and diverse combinations of them, [7,8] have been proposed. Uniform repeater insertion is an effective technique for driving long interconnects and the authors in Ref.…”

“…Based on RC delay model, crosstalk and delay are optimized simultaneously by wire sizing, wire spacing and repeater insertion in Ref. [8].…”