Interconnect Lifetime Prediction for Reliability-Aware Systems

Lu, Zhijian; Huang, Wei; Stan, Mircea R.; Skadron, Kevin; Lach, John

doi:10.1109/tvlsi.2007.893578

Cited by 40 publications

(15 citation statements)

References 29 publications

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“…Overall, the EM phenomenon for high current densities can result to the metal failure, irrespective of the metal in question [125][126][127]. Therefore, the EM can be compensated by using a laminating barrier such as tungsten (W) and titanium(Ti).…”

Section: Electro-migration (Em)mentioning

confidence: 99%

Reliability Modeling and Mitigation for Embedded Memories

Agbo

Taouil

Hamdioui

2019

2019 IEEE International Test Conference (ITC)

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Complementary Metallic Oxide Semiconductor (CMOS) technology scaling enhances the performance, transistor density, functionality, and reduces cost and power consumption. However, scaling causes significant reliability challenges both from a manufacturing and operational point of view. Obtaining reliable memories require accurate understanding of the impact of aging (such as Bias temperature instability (BTI)) on individual memory components and how they interact with each other. In this dissertation, two types of challenges are addressed, which are related to BTI aging and partially to mitigation schemes: one related to the aging of sense amplifier and another one to the aging of read path and write path. Analysis of aging impact on different memory sense amplifiers-The analysis of BTI impact on various memory sense amplifier (SA) designs was performed, while taking into account two BTI models (i.e., Atomistic and RD model), different technology nodes (i.e., 90, 65, 45, 32, 22, and 16 nm), and different workloads. First, the analysis and comparison of RD and Atomistic models impact on the SA were performed. The results show that the atomistic trap-based BTI model is more accurate than the RD model. Second, the investigation of BTI impact on the drain-input latch type SA for various technology nodes and supply voltages was performed. The result shows that as technology scales down, the impact of BTI on sensing delay increases, while the sensing voltage decreases, causing less robust and reliable memory sense amplifier. The result also shows that increase in supply voltage compensates the BTI degradation. Third, an accurate technique was proposed and characterized for the integral impact of BTI and voltage temperature variation on the memory standard latch type SA for various technology nodes and workloads. The results show that the degradation is strongly dependent on workload and temperature. Fourth, in addition to the latter, the impact of process variation at timezero was incorporated and analyzed. The results show that the SA sensing delay degradation is more significant at lower nodes and could lead to read failures at lower power supply. This reveals that there must be a tradeoff between performance and reliability. Fifth, an accurate methodology was proposed to quantify the impact of variability on the memory SA offset-voltage for both time-zero and time-dependent variability. The results show that the impact on the offset voltage specification is significant for aging time-dependent variability. Sixth, on top of the latter, the sensitivity of the SA and its failure rate were analyzed for five process corners (i.e., Nominal, Fast-Fast, Fast-Slow, Slow-Fast, and Slow-Slow). The results show that balanced workloads result in a significant low offset voltage specification. Finally, the impact of aging was analyzed and compared, while considering different supply voltages, temperatures, and SA designs. The results show that the High Performance SA degrades faster than other SA types, irrespective of the workloa...

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Section: Electro-migration (Em)mentioning

confidence: 99%

Reliability Modeling and Mitigation for Embedded Memories

Agbo

Taouil

Hamdioui

2019

2019 IEEE International Test Conference (ITC)

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“…This is increasingly because of thermally-induced accelerated failure rates. For example, one analysis of electromigration-related failure of VLSI interconnect suggests that the mean time to failure is inversely related to the operating temperature [8]:…”

Section: Implications For Reliabilitymentioning

confidence: 99%

Adaptive fault-tolerance fault-tolerance for cyber-physical systems

Krishna

Koren

2013

2013 International Conference on Computing, Networking and Communications (ICNC)

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Cyber-physical systems are increasingly used in lifecritical applications, where the probability of catastrophic failure has to be kept below very low levels. Massive fault-tolerance has been used to mask failure to achieve such low levels. However, fault-tolerance is expensive. We argue here that the fault-tolerance needs of an application change depending on its current position in its state space and the range of control inputs that can be applied. We illustrate the applicability of such an approach using the inverted pendulum as a case-study, and discuss its potential benefits.

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“…The most representative ones include time-dependent dielectric breakdown (TDDB) in the gate oxides, electromigration (EM) and stress migration (SM) in the interconnects, and negative bias temperature instability (NBTI) stresses that shift PMOS transistor threshold voltages. Many widely accepted reliability models for the above failure mechanisms at device and circuit level have been proposed and empirically validated by academia and industry [19], [20], [21], [22], [23], [24], and it is shown that they are strongly related to the temperature and voltage applied to the circuit.…”

Section: Ic Lifetime Reliabilitymentioning

confidence: 99%

On Task Allocation and Scheduling for Lifetime Extension of Platform-Based MPSoC Designs

Huang

Yuan

2011

IEEE Trans. Parallel Distrib. Syst.

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Abstract-With the relentless scaling of semiconductor technology, the lifetime reliability of today's multiprocessor system-on-a-chip (MPSoC) designs has become one of the major concerns for the industry. Without explicitly taking this issue into consideration during the task allocation and scheduling process, existing works may lead to imbalanced aging rates among processors, thus reducing the system's service life. To tackle this problem, in this paper, we propose an analytical model to estimate the lifetime reliability of multiprocessor platforms when executing periodical tasks, and we present a novel task allocation and scheduling algorithm that is able to take the aging effects of processors into account, based on the simulated annealing technique. In addition, to speed up the annealing process, several techniques are proposed to simplify the design space exploration process with satisfactory solution quality. Experimental results on various hypothetical multiprocessors and task graphs show that significant system lifetime extension can be achieved by using the proposed approach, especially for heterogeneous platforms with large task graphs.Index Terms-Lifetime reliability, aging effect, multiprocessor system-on-a-chip, task allocation and scheduling.

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Interconnect Lifetime Prediction for Reliability-Aware Systems

Cited by 40 publications

References 29 publications

Reliability Modeling and Mitigation for Embedded Memories

Reliability Modeling and Mitigation for Embedded Memories

Adaptive fault-tolerance fault-tolerance for cyber-physical systems

On Task Allocation and Scheduling for Lifetime Extension of Platform-Based MPSoC Designs

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