Interconnect performance and scaling strategy at 7 nm node

Chen, James Hsueh-Chung; Standaert, T.; Alptekin, Emre; Spooner, T.; Paruchuri, Vamsi

doi:10.1109/iitc.2014.6831843

Cited by 27 publications

(7 citation statements)

References 12 publications

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“…3 wt% aqueous colloidal silica dispersions (Nexsil 35 A) with the abrasive of average diameter ∼35 nm, obtained from Nyacol Nano Technologies, were used for all the polishing experiments along with reagent grade chemicals obtained from Sigma-Aldrich. The pH of the aqueous dispersions containing the additives was adjusted using HNO 3 or KOH as necessary. Co powder, spherical, ∼0.75 mm in diameter on average, was obtained from Alfa Aeasar and used for preparing samples for spectroscopic measurements.…”

Section: Methodsmentioning

confidence: 99%

“…These include increasing resistivity with decreasing thickness, 1 non-conformal deposition at narrow trench widths ∼20 nm or less, 2 and scaling limitations of the diffusion barrier/liner. 3 This led to the investigation of new trench filling materials. Cobalt is a promising alternative to meet the challenges of interconnect lines at these lower nodes for the first two metal layers M1 and M2, due to its lower resistivity at smaller dimensions (∼10 nm) compared to copper.…”

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confidence: 99%

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Citric Acid as a Complexing Agent in Chemical Mechanical Polishing Slurries for Cobalt Films for Interconnect Applications

Popuri

Sagi

Alety

et al. 2017

ECS J. Solid State Sci. Technol.

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A colloidal silica-based slurry (3-10 wt%) containing H 2 O 2 (1 wt%) and citric acid (50 mM) was found to polish chemical vapordeposited (CVD) cobalt (Co) films with removal rates (RRs) of ∼180-500 nm/min and a dissolution rate (DR) of ∼0 nm/min at pH 8 along with an RMS roughness of ∼0.5 nm and a corrosion current of ∼50 μA/cm 2 . Our results suggest that, in the presence of H 2 O 2 , the Co film surface was covered with a passive film of CoO in acidic conditions and Co 3 O 4 in alkaline conditions. However, in the presence of H 2 O 2 and citric acid in acidic conditions, formation of the soluble complex [Co(C 6 H 5 O 7 ) 2 ] 3− from abraded Co enhanced the RRs significantly. The roles of H 2 O 2 , citric acid, and silica abrasives as well as the pH on the Co material removal process are discussed and a removal mechanism is proposed. Two inhibitors namely, 1, 2, 4-Triazole (TAZ) and Benzotriazole (BTA), were tested in the presence of 50 mM citric acid at pH 8 but were found to be ineffective even at concentrations of 100 mM in reducing the E corr of Co-Ti couple to minimize galvanic corrosion that is essential when the Co/Ti structure is polished after the removal of bulk of Co and requires further study. Sub-10 nm devices face several challenges with copper as an interconnect material for back-end-of-the-line (BEOL) processes during the manufacture of integrated circuits. These include increasing resistivity with decreasing thickness, 1 non-conformal deposition at narrow trench widths ∼20 nm or less, 2 and scaling limitations of the diffusion barrier/liner.3 This led to the investigation of new trench filling materials. Cobalt is a promising alternative to meet the challenges of interconnect lines at these lower nodes for the first two metal layers M1 and M2, due to its lower resistivity at smaller dimensions (∼10 nm) compared to copper. [4][5][6] Kamineni et al. 7 proposed the use of chemical vapor deposited (CVD) cobalt to replace the widely used tungsten for local interconnects for 10 nm and smaller nodes. They emphasized two main advantages of CVD Co metallization which are a) CVD Co precursors do not damage the Ti liner enabling barrier scaling and b) it achieves void free fill in high aspect ratio features without defects, something that is difficult to achieve with a conventional physical vapor deposited (PVD) Co process. 8,9 Hence, CVD-based Co metallization is an attractive option for the technology nodes below 10 nm.CVD-based cobalt has also gained prominence in the advanced copper interconnects below 22 nm as liner [10][11][12][13][14][15][16][17] to improve adhesion between the barrier (TaN, TiN) and Cu seed layer where the Co film thickness is only ∼2 nm. Several authors 18-26 have investigated cobalt polishing for such applications where RR requirements are typically <20 nm/min and Co loss due to corrosion has to be as close to zero as possible, since even a minute loss of Co material can degrade the device reliability significantly. Hence, since the potential gap between Co and Cu is a large ∼0...

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Section: Methodsmentioning

confidence: 99%

mentioning

confidence: 99%

Citric Acid as a Complexing Agent in Chemical Mechanical Polishing Slurries for Cobalt Films for Interconnect Applications

Popuri

Sagi

Alety

et al. 2017

ECS J. Solid State Sci. Technol.

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“…At 10nm however, the cost of BEOL has increased by almost 2 times as compared to that at 28nm node. Moreover [4] focuses on the interconnect delay from a 10nm node to a 7nm node, for wire length above 20um, indicating that a 20% reduction in Metal 3 wire resistance can result in more than a 10% increase in performance.…”

Section: Related Workmentioning

confidence: 99%

Self-Timed Write Aid Circuit for Tall Memories in Advanced CMOS Technologies

Nautiyal

Singla

Maiti

et al. 2021

2021 IEEE International Symposium on Circuits and Systems (ISCAS)

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As CMOS technology scales with complex lithography, metal resistance increases. Specifically, at hightemperatures IR drop limits the performance and impacts the yield of CMOS circuits. For SRAM, bitline resistance limits the writeability of bitcells. This paper proposes a self-timed Write Aid circuit that helps the write driver by discharging the bitline from its opposite side. The use of this aid circuit at performance worst corner, improves write time by more than 40%. For a fixed wordline pulse width of 250ps, there is around 1.5 sigma write yield improvement at 0.765v operation. The proposed circuit has been implemented and Si validated in 7nm technology.

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“…Therefore, the effects of interconnect parasitic elements are no longer second order effects. They are now dominating the overall circuit performance [1]- [3]. As a result, it is very important to consider the parasitic effects during placement and routing processes to reduce the overall turn-around-time of a circuit design and improve the yield.…”

Section: Introductionmentioning

confidence: 99%

RC Parasitic-Aware Layout Analysis and Routing Optimization Methodology

Abouelyazid

Hammouda²,

Ismail

2022

IEEE Access

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A parasitic-aware routing optimization and analysis methodology for integrated circuits is developed based on an incremental parasitic extraction and a fast optimization methodology. Existing routing optimization methodologies rely on many circuit simulations, detailed sensitivity analysis, and inefficient simple parasitic models to optimize routes. Moreover, they do not provide a mechanism to help layout designers in identifying problematic layout geometries that have a bad impact on a route's performance. The proposed methodology works on overcoming such problems by providing three features. First, it provides novel sensitivity circuit models to analyze the integrity of signals in layout routes. Such circuit models are based on an accurate matrix circuit representation, a cost function, and an accurate parasitic sensitivity extraction. The circuit models identify critical parasitic elements along with the corresponding layout geometries in a certain route, where they measure the sensitivity of a route's performance to corresponding layout geometries very fast. Therefore, they can correlate the problems of a route's performance to specific layout geometries. Second, the proposed methodology uses a nonlinear programming technique to optimize problematic routes with pre-determined degrees of freedom using the proposed circuit models. Third, the proposed methodology uses a novel incremental parasitic extraction method to extract parasitic elements of modified geometries efficiently. The incremental extraction is used as a part of the routing optimization process to improve the optimization runtime and increase the optimization accuracy. The proposed methodology is tested over different designs of 7nm and 65nm process nodes. The results show that the proposed methodology managed to identify and optimize the problematic geometries in critical routes efficiently with up to 10% performance improvements and a speedup of 3 to 9X as compared to traditional template-based methods.

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Interconnect performance and scaling strategy at 7 nm node

Cited by 27 publications

References 12 publications

Citric Acid as a Complexing Agent in Chemical Mechanical Polishing Slurries for Cobalt Films for Interconnect Applications

Citric Acid as a Complexing Agent in Chemical Mechanical Polishing Slurries for Cobalt Films for Interconnect Applications

Self-Timed Write Aid Circuit for Tall Memories in Advanced CMOS Technologies

RC Parasitic-Aware Layout Analysis and Routing Optimization Methodology

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