Interconnect performance estimation models for design planning

Cong, Jason; Pan, Zhigang

doi:10.1109/43.924827

Cited by 67 publications

(48 citation statements)

References 49 publications

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“…I think that no major benefits can be derived with this timing-driven router. The majority of the nets (60% ∼ 70%) have only one sink [21]. For two-pin nets the routing solution is not different using the routability-driven router.…”

Section: Zelix Mpga Routing Algorithmmentioning

confidence: 99%

Automated Conversion From Lut-Based FPGAs to LUT-Based MPGAs

Veredas

Pfleiderer

2006

2006 International Conference on Field Programmable Logic and Applications

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Field-programmable gate-arrays (FPGAs) are used for application-specific standard product (ASIC) prototyping or small volume products. In medium to large volume products, the prototyping design or the small volume product is converted to another integrated circuit (IC) structure such as maskprogrammable gate arrays (MPGAs). MPGAs are of growing importance because of the increase of design cost, and turnaround times in ultra-deep submicron technologies which mostly impact ASICs. Several design methodologies have been proposed in recent years for converting an evaluated FPGA prototype-design into an MPGA. The MPGA design uses potentially less area, delay, and dynamic power consumption than the FPGA design.In a conversion from an FPGA design, the engineer looks for a simple flow to minimize time-to-market. It is well known that the most time consuming process in an IC design is verification. Formal verification checks the functionality of the designed circuit. Physical verification checks the timing (and in same cases the power consumption) of the designed circuit. Formal verification is simplified if the same gate-level netlist of the FPGA is used in the conversion. Simplification of physical verification is possible by exploiting the regularity in the IC layout.In this thesis, two new Look-Up Table-

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Section: Zelix Mpga Routing Algorithmmentioning

confidence: 99%

Automated Conversion From Lut-Based FPGAs to LUT-Based MPGAs

Veredas

Pfleiderer

2006

2006 International Conference on Field Programmable Logic and Applications

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“…Table V lists the ratios of the performance results by comparing MCAS versus Synopsys BC. 7 The two flows achieve the similar resource cost and scheduled clock cycles. However, MCAS flow obtains a 21% improvement in clock period and a 29% improvement in total latency on average.…”

Section: Mcas Versus Synopsys Behavioral Compiler (Bc)mentioning

confidence: 99%

Architecture and Synthesis for On-Chip Multicycle Communication

Cong

Fan

Han

et al. 2004

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-For multigigahertz designs in nanometer technologies, data transfers on global interconnects take multiple clock cycles. In this paper, we propose a regular distributed register (RDR) microarchitecture, which offers high regularity and direct support of multicycle on-chip communication. The RDR microarchitecture divides the entire chip into an array of islands so that all local computation and communication within an island can be performed in a single clock cycle. Each island contains a cluster of computational elements, local registers, and a local controller. On top of the RDR microarchitecture, novel layout-driven architectural synthesis algorithms have been developed for multicycle communication, including scheduling-driven placement, placement-driven simultaneous scheduling with rebinding, and distributed control generation, etc. The experimentation on a number of real-life examples demonstrates promising results. For data flow intensive examples, we obtain a 44% improvement on average in terms of the clock period and a 37% improvement on average in terms of the final latency, over the traditional flow. For designs with control flow, our approach achieves a 28% clock-period reduction and a 23% latency reduction on average.

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“…A fullsystem switching-activity simulator was used during powerconsumption computation. Wire power consumption and wire delay were calculated based on the wire capacitances estimated using Cong's and Pan's technique [46] and the wire-length information from the floorplanner of the high-level-synthesis design tools. As described in Section III, both logic and wire delays were calculated to determine whether each design meets its timing requirements.…”

Section: A Benchmarksmentioning

confidence: 99%

Unified Incremental Physical-Level and High-Level Synthesis

Wang

Dick

et al. 2007

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-Achieving design closure is one of the biggest challenges for modern very large-scale integration system designers. This problem is exacerbated by the lack of high-level designautomation tools that consider the increasingly important impact of physical features, such as interconnect, on integrated circuit area, performance, and power consumption. Using physical information to guide decisions in the behavioral-level stage of system design is essential to solve this problem. In this paper, we present an incremental floorplanning high-level-synthesis system. This system integrates high-level and physical-design algorithms to concurrently improve a design's schedule, resource binding, and floorplan, thereby allowing the incremental exploration of the combined behavioral-level and physical-level design space. Compared with previous approaches that repeatedly call loosely coupled floorplanners for physical estimation, this approach has the benefits of efficiency, stability, and better quality of results. The average CPU time speedup resulting from unifying incremental physical-level and high-level synthesis is 24.72× and area improvement is 13.76%. The low power consumption of a state-of-the-art low-power interconnect-aware high-levelsynthesis algorithm is maintained. The benefits of concurrent behavioral-level and physical-design optimization increased for larger problem instances.Index Terms-Behavioral synthesis, floorplanning, low power design.

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Interconnect performance estimation models for design planning

Cited by 67 publications

References 49 publications

Automated Conversion From Lut-Based FPGAs to LUT-Based MPGAs

Automated Conversion From Lut-Based FPGAs to LUT-Based MPGAs

Architecture and Synthesis for On-Chip Multicycle Communication

Unified Incremental Physical-Level and High-Level Synthesis

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