Interconnect Solutions for Virtualized Field-Programmable Gate Arrays

Yazdanshenas, Sadegh; Betz, Vaughn

doi:10.1109/access.2018.2806618

Cited by 24 publications

(15 citation statements)

References 14 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Most common interconnect topologies for CGRAs include nearest-neighbour style [9], [32], and island-style [33]- [35]. Overall, CGRAs, use either static, dynamically changeable point-to-point connection [39], or network on chip (NoC) communication [40]- [44]. These network implementation methods provide a trade-off between implementation cost and flexibility (e.g., for providing more or less complex communication patterns).…”

Section: A Overlaysmentioning

confidence: 99%

“…These network implementation methods provide a trade-off between implementation cost and flexibility (e.g., for providing more or less complex communication patterns). However, for virtualization, recent lightweight soft packet switched Network-on-Chip (NoC) (e.g., Hoplite [43]) and especially hard NoC [44] seem promising solutions to provide resourceefficient and high-speed interconnects for programmable overlays.…”

Section: A Overlaysmentioning

confidence: 99%

See 1 more Smart Citation

A Survey on FPGA Virtualization

Vaishnav

Pham

Koch

2018

2018 28th International Conference on Field Programmable Logic and Applications (FPL)

View full text Add to dashboard Cite

FPGA accelerators are being applied in various types of systems ranging from embedded systems to cloud computing for their high performance and energy efficiency. Given the scale of deployment, there is a need for efficient application development, resource management, and scalable systems, which make FPGA virtualization extremely important. Consequently, FPGA virtualization methods and hardware infrastructures have frequently been proposed in both academia and industry for addressing multi-tenancy execution, multi-FPGA acceleration, flexibility, resource management and security. In this survey, we identify and classify the various techniques and approaches into three main categories: 1) Resource level, 2) Node level, and 3) Multi-node level. In addition, we identify current trends and developments and highlight important future directions for FPGA virtualization which require further work.

show abstract

Section: A Overlaysmentioning

confidence: 99%

Section: A Overlaysmentioning

confidence: 99%

A Survey on FPGA Virtualization

Vaishnav

Pham

Koch

2018

2018 28th International Conference on Field Programmable Logic and Applications (FPL)

View full text Add to dashboard Cite

show abstract

“…FPGA virtualization, however, degrades the performance of applications, congests routing, and more importantly, limits the area of applications [19]. This scheme also suffers from security challenges [20].…”

Section: Introductionmentioning

confidence: 99%

Workload-Aware Opportunistic Energy Efficiency in Multi-FPGA Platforms

Salamat

Khaleghi

Imani

et al. 2019

2019 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

View full text Add to dashboard Cite

The continuous growth of big data applications with high computational and scalability demands has resulted in increasing popularity of cloud computing. Optimizing the performance and power consumption of cloud resources is therefore crucial to relieve the costs of data centers. In recent years, multi-FPGA platforms have gained traction in data centers as lowcost yet high-performance solutions particularly as acceleration engines, thanks to the high degree of parallelism they provide. Nonetheless, the size of data centers workloads varies during service time, leading to significant underutilization of computing resources while consuming a large amount of power, which turns out as a key factor of data center inefficiency, regardless of the underlying hardware structure. In this paper, we propose an efficient framework to throttle the power consumption of multi-FPGA platforms by dynamically scaling the voltage and hereby frequency during runtime according to prediction of, and adjustment to the workload level, while maintaining the desired Quality of Service (QoS). This is in contrast to, and more efficient than, conventional approaches that merely scale (i.e., power-gate) the computing nodes or frequency. The proposed framework carefully exploits a pre-characterized library of delay-voltage, and power-voltage information of FPGA resources, which we show is indispensable to obtain the efficient operating point due to the different sensitivity of resources w.r.t. voltage scaling, particularly considering multiple power rails residing in these devices. Our evaluations by implementing state-of-the-art deep neural network accelerators revealed that, providing an average power reduction of 4.0×, the proposed framework surpasses the previous works by 33.6% (up to 83%).

show abstract

“…Data transfers in most of the high-performance architectures are limited by memory hierarchy and communication architecture, as summarized in [19,20]. Exploiting communication architecture suggests the use of NoC, an effective replacement for buses or dedicated links in a system with large number of processing cores [21,22]. NoC is composed of several tunable parameters like network architecture, algorithm, network topology and flow control.…”

Section: Revisiting the Network On Chip Evaluation Toolsmentioning

confidence: 99%

“…NoC are also found abundantly in CGRAs, some examples are [64][65][66][67]. NoC based architectures offer flexibility at the cost of higher implementation cost, but some works, like Hoplite soft NoC [67] and hard NoC [22], offer resource-efficient fast interconnects. Although an effort to reduce the cost by mapping the overlay look-up tables and multiplexers to the FPGA fabric has been achieved in [68].…”

Section: Overlaysmentioning

confidence: 99%

Revisiting the High-Performance Reconfigurable Computing for Future Datacenters

2020

View full text Add to dashboard Cite

Modern datacenters are reinforcing the computational power and energy efficiency by assimilating field programmable gate arrays (FPGAs). The sustainability of this large-scale integration depends on enabling multi-tenant FPGAs. This requisite amplifies the importance of communication architecture and virtualization method with the required features in order to meet the high-end objective. Consequently, in the last decade, academia and industry proposed several virtualization techniques and hardware architectures for addressing resource management, scheduling, adoptability, segregation, scalability, performance-overhead, availability, programmability, time-to-market, security, and mainly, multitenancy. This paper provides an extensive survey covering three important aspects—discussion on non-standard terms used in existing literature, network-on-chip evaluation choices as a mean to explore the communication architecture, and virtualization methods under latest classification. The purpose is to emphasize the importance of choosing appropriate communication architecture, virtualization technique and standard language to evolve the multi-tenant FPGAs in datacenters. None of the previous surveys encapsulated these aspects in one writing. Open problems are indicated for scientific community as well.

show abstract

Interconnect Solutions for Virtualized Field-Programmable Gate Arrays

Cited by 24 publications

References 14 publications

A Survey on FPGA Virtualization

A Survey on FPGA Virtualization

Workload-Aware Opportunistic Energy Efficiency in Multi-FPGA Platforms

Revisiting the High-Performance Reconfigurable Computing for Future Datacenters

Contact Info

Product

Resources

About