Interconnection Network for Structured Low-Density Parity-Check Decoders

Decoding of Quasi-cyclic LDPC Codes Using an On-the-Fly Computation

“…So to be able to accommodate different shifts needed for WiMax LDPC codes, we can use a Benes network as in [19], which is of complexity 2log 2(M) -1 stages of M 2-in-I multiplexers. A memory can be used to store control inputs needed for different shifts in case of supporting one expansion factor [3], [19]. The authors in [3] use Omega network, which is less complex than Benes network [19].…”

VLSI Architectures for Layered Decoding for Irregular LDPC Codes of WiMax

“…[2] uses Omega network, which is less complex than Benes network [15]. However both [12] and [15] So this approach clearly will not work. We propose a simpler approach to generate the control signals using a Master-Slave Benes router (Fig.…”

“…The implementation has a performance penalty of less than 0. 15 . The distinction of this architecture is that a near optimal minimal number of clock cycles are achieved when the expansion factor is a multiple of parallelization of the decoder-Note that some codes support processing of two layers in parallel and the decoder can accommodate this if sufficient parallelism is available as can be seen from Fig.…”

“…So to be able to accommodate different shifts needed, we can use a Benes network as in [15], which is of complexity 1 ) ( 2 log 2 − M stages of M 2-in-1 multiplexers. A memory can be used to store control inputs needed for different shifts in case of supporting one expansion factor [2], [15].…”

“…A memory can be used to store control inputs needed for different shifts in case of supporting one expansion factor [2], [15]. [2] uses Omega network, which is less complex than Benes network [15].…”