Interface circuit for capacitive accelerometer

Paemel, M. Van

doi:10.1016/0250-6874(89)80055-1

Cited by 15 publications

(1 citation statement)

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“…Various schemes were employed to implement the feedback approach. These include phase-locked loop (PLL) [Matsumoto 1993], pulse width modulation [Suzuki 1990], gain feedback [Paemel 1989], [Boxenhorn 1990], ], [Kampen 1994], [Kuehnel 1994], [Kromer 1995], [Zimmermann 1995], [Burstein 1996], [Chau 1996], and sigma-delta modulators [Henrion 1990], [Yun 1992], [Smith 1994], [Lu 1995], [Boser 1996], [Spangler 1996, [Wuestling 1997], ], [Kraft 1998a], [Lemkin 1999], [Yazdi 1999…”

Section: Review Of Accelerometer System Architecturesmentioning

confidence: 99%

A signal-conditioning chip for accelerometer applications

Lee¹

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This thesis presents a low-cost, high-performance, fully-integrated interface and signalconditioning ASIC (Application-Specific Integrated Circuits) for capacitive-based automotive accelerometers. The ASIC is a mixed-signal system, which comprises a switched-capacitor (SC) sense amplifier, a two-stage (SC and continuous-time) filter, a scaling output stage and a clocking module, with on-chip calibration capability. The design foundation is based on a new "injection-nulling switch" (INS). The INS has been experimentally verified to exhibit error less than 25 uV in sample-and-hold (S/H) circuit and demonstrated to be insensitive to variation of process parameters. For the ASIC design, the INS allows for simplified topology of SC front-end sense amplifier and subsequent SC building blocks without jeopardizing the performance via counteracting the impact of charge injection and clock feedthrough effects on sensitivity, resolution and offset. This has resulted in reducing power consumption of system IC significantly. The clocking module is a new programmable low-frequency clock generator based on the Miller ring oscillator that offers wide-tuning range whilst using small capacitance values, with jitter less than 300 ps at ±10% variation in 5 V supply. A new orthogonal fusible link structure design is incorporated in the calibration circuits to improve its reliability. The development of the ASIC is based on a new sensor model, which takes into account of sensor parasitic effects. The ASIC was fabricated using a standard 0.6 um CMOS technology with a die size of 2.8 mm by 2.3 mm. The accelerometer was implemented in a two-chip integrated 16-pin DIL IC, where the ASIC was bonded to a ±50 g sensing element. The IC has been experimentally tested. It has achieved a low power consumption of 10 mW (2 mA at 5 V), maximum noise root spectral density of 11.87 uV/VHz (rms noise root spectral density of 0.187 mg/VHz) at 15.63 Hz, a signal-to-noise dynamic range of 77 dB for 500 Hz bandwidth and 74 dB for 1 kHz bandwidth, and maximum clock noise of 1.562 mV.

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