Interface Engineering by PVD-Based In-Situ Fabrication Method for Advanced Metal/High-k Gate Stacks

Abstract

We fabricated high-quality silicate gate dielectrics by utilizing a solid phase interface reaction (SPIR) between ultrathin metal layers and SiO 2 underlayers. Metal diffusion to the SiO 2 underlayer forms a high-quality silicate interlayer, and preserving the initial SiO 2 /Si bottom interface ensures good electrical properties. The Hf silicate dielectrics were fabricated by the SPIR method using Hf layers less than 0.5-nm-thick that were fully consumed by interface reactions, resulting in Hf silicate layers that remained amorphous after activation annealing. The superior electrical properties of the poly-Si/HfSixOy/SiO 2 /Si MOSFETs were demonstrated through low leakage current and high electron mobility. We also recently proposed a novel in-situ fabrication method that continuously fabricates high-k dielectrics using SPIR and metal electrodes with a low-damage sputtering system. We investigated structural and electrical properties of metal/high-k gate stacks and demonstrated the effectiveness of the in-situ method in improving electrical properties.

High Performance Gate-First pMISFET with TiN/HfSiON Gate Stacks Fabricated with PVD-Based In-Situ Method

“…This paper reviews the physical and electrical characteristics of TiN/HfSiON gate stacks for pMISFETs fabricated with the PVD-based in-situ method. The concept of this method have already been reported in the references (22,23), and it is as follows; PVDgrown metal-Hf layer on SiO 2 underlayer was fully consumed by annealing of solid phase interface reaction (SPIR) to form Hf-silicate (24,25), and TiN film was continuously grown on the Hf-silicate with low-damage PVD without exposure to air (22,23). Then, it can minimize the impurities both within HfSiON layer and metal/high-k interface.…”

High Performance Gate-First pMISFET with TiN/HfSiON Gate Stacks Fabricated with PVD-Based In-Situ Method

“…Then, PVD-based in-situ method for TiN/HfSiON stack is much attractive because it can minimize the impurities both within HfSiON layer and metal/high-k interface. This method is as follows; PVD-grown metal-Hf layer on SiO 2 underlayer was fully consumed by annealing of solid phase interface reaction (SPIR) to form Hf-silicate [6], and TiN film was continuously grown on the Hf-silicate with low-damage PVD without exposure to air [7]. In this work, we investigated the effects of this PVD-based in-situ method on the pMISFET properties, comparing with the usual ex-situ CVD methods.…”