Interface-State Modeling of $\hbox{Al}_{2}\hbox{O}_{3}$ –InGaAs MOS From Depletion to Inversion

Abstract

This paper presents a detailed analysis of the multifrequency capacitance-voltage and conductance-voltage data of Al 2 O 3 /n-InGaAs MOS capacitors. It is shown that the widely varied frequency dependence of the data from depletion to inversion can be fitted to various regional equivalent circuits derived from the full interface-state model. In certain regions, incorporating bulk-oxide traps in the interface-state model enables better fitting of data. By calibrating the model with experimental data, the interface-state density and the trap time constants are extracted as functions of energy in the bandgap, from which the stretch-out of gate voltage is determined. It is concluded that the commonly observed decrease of the 1-kHz capacitance toward stronger inversion is due to the increasing time constant for traps to capture majority carriers at the inverted surface.Index Terms-Bulk-oxide trap, D it , III-V, interface trap, MOS.

Electrical spin injection in silicon and the role of defects

“…5(a), 5(c), and 5(e), in all systems, we clearly see the presence of low bias peaks that disappear when increasing the excitation frequency. This observation is consistent with the presence of charge trapping into interface states [37]. At higher temperature, the electronic confinement of interface states can be thermally overcome as shown in Figs.…”

Multi-frequency inversion-charge pumping for charge separation and mobility analysis in high-k/InGaAs metal-oxide-semiconductor field-effect transistors

“…A distance (x) for the spatial location of the border traps relative to the In 0.53 Ga 0.47 As interface can be estimated using the relationship 33 x ¼ k lnðt=sÞ; (7) where k is the attenuation coefficient and t is the tunnelling time. Assuming a k value within the typical range of 9.8 Â 10 À9 -1.25 Â 10 À8 cm reported for the Al 2 O 3 / In 0.53 Ga 0.47 As interface [16][17][18]21,30 and considering that N CP saturation is reached at t $ 5 ls (Fig. 6), we obtain a distance x of about 1.6-2.1 Å from the interface.…”

“…Recent studies have indicated the presence of border traps in high-k/InGaAs MOS structures using C-V, [15][16][17][18][19] charge pumping 20 and high-frequency transconductance 21 measurements. Evidence of the presence of border traps can also be observed in an I d -V g characteristic, where it is manifest as a hysteresis loop.…”

A novel technique exploiting C–V, G–V and I–V simulations to investigate defect distribution and native oxide in high-κ dielectrics for III–V MOSFETs

“…Fig. 9 shows the Dit profiles reported in the literature [10][11][12][13][14][15], which are compared to the effective density of interfacial states obtained by integrating the extracted N bt (E,z) along the oxide thickness, z, at any energy. The extracted effective Dit profile shows values comparable with those reported in the literature on similar devices.…”