Interface trap and interface depletion in lattice-mismatched GaInAs/GaAs heterostructures

Choi, Y. W.; Xie, Kai; Kim, H. M.; Wie, C. R.

doi:10.1007/bf02666016

Cited by 9 publications

(1 citation statement)

References 19 publications

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“…In this case, the electrical characteristics of device are deteriorated by the local increase of electric field in the thin area [12,13]. In addition, the interface roughness influences the interface defect formation by intensifying the lattice constant mismatch between the layers [14,15]. It is well known that the shallow interface traps between TO and CTL affects SONOS flash memory performance [16,17].…”

Section: Conditionmentioning

confidence: 99%

Physical and Electrical Analysis of Poly-Si Channel Effect on SONOS Flash Memory

Jeong

Sung

et al. 2021

Micromachines

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In this study, polycrystalline silicon (poly-Si) is applied to silicon-oxide-nitride-oxide-silicon (SONOS) flash memory as a channel material and the physical and electrical characteristics are analyzed. The results show that the surface roughness of silicon nitride as charge trapping layer (CTL) is enlarged with the number of interface traps and the data retention properties are deteriorated in the device with underlying poly-Si channel which can be serious problem in gate-last 3D NAND flash memory architecture. To improve the memory performance, high pressure deuterium (D2) annealing is suggested as a low-temperature process and the program window and threshold voltage shift in data retention mode is compared before and after the D2 annealing. The suggested curing is found to be effective in improving the device reliability.

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Section: Conditionmentioning

confidence: 99%

Physical and Electrical Analysis of Poly-Si Channel Effect on SONOS Flash Memory

Jeong

Sung

et al. 2021

Micromachines

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Study of Metal–Dielectric Interface for Improving Electrical Properties and Reliability of DRAM Capacitor

Lim

Choi

Cho

et al. 2022

Adv Materials Technologies

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The interface between a dielectric thin film and a metal electrode is studied to improve reliability as well as electrical properties of the metal–insulator–metal (MIM) capacitor in dynamic random‐access memory (DRAM) devices. The interfacial layers between a dielectric thin film and a metal electrode play important functional roles such as increasing the electrical barrier or preventing oxygen defects in high‐k dielectrics. By introducing an electrical barrier layer or a sacrificial layer at the metal–dielectric interface for engineering the electronic band, lattice, or dipole, various effects could be confirmed such as the conduction band offset (CBO), bandgap or mismatch modulation for controlling the dielectric loss depending on the AC frequency or leakage current of MIM capacitors. Upon the insertion of Al2O3 as an electrical barrier layer, CBO increased because of the band engineering. Further, upon the insertion of TiO2 as a sacrificial layer at the interface, CBO increased because of the dipole formation at the interface, attributed to the difference in electronegativity. Thus, a robust MIM capacitor for DRAM that maintains a low leakage current and has improved reliability which is realized using the proper combination of interfacial layers.

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Impact of Defects on the Performance of High-Mobility Semiconductor Devices

Simoen

2018

High Mobility Materials for CMOS Applications

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Interface trap and interface depletion in lattice-mismatched GaInAs/GaAs heterostructures

Cited by 9 publications

References 19 publications

Physical and Electrical Analysis of Poly-Si Channel Effect on SONOS Flash Memory

Physical and Electrical Analysis of Poly-Si Channel Effect on SONOS Flash Memory

Study of Metal–Dielectric Interface for Improving Electrical Properties and Reliability of DRAM Capacitor

Impact of Defects on the Performance of High-Mobility Semiconductor Devices

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