Interface trap density metrology from sub-threshold transport in highly scaled undoped Si n-FinFETs

Abstract

Channel conductance measurements can be used as a tool to study thermally activated electron transport in the sub-threshold region of state-of-art FinFETs. Together with theoretical TightBinding (TB) calculations, this technique can be used to understand the evolution of source-tochannel barrier height (E b ) and of active channel area (S) with gate bias (Vgs). The quantitative difference between experimental and theoretical values that we observe can be attributed to the interface traps present in these FinFETs. Therefore, based on the difference between measured and calculated values of (i) S and (ii) |∂E b /∂Vgs| (channel to gate coupling), two new methods of interface trap density (Dit) metrology are outlined. These two methods are shown to be very consistent and reliable, thereby opening new ways of analyzing in situ state-of-the-art multi-gate FETs down to the few nm width limit. Furthermore, theoretical investigation of the spatial current density reveal volume inversion in thinner FinFETs near the threshold voltage.

Enhancement of n‐Type Organic Field‐Effect Transistor Performances through Surface Doping with Aminosilanes

“…However, it needs to be pointed out that Equation further requires a negligible density of deep trap states in the bulk material, a condition that in our case likely is not well fulfilled, given the fact that an electrically active material is diffusing into the semiconductor film. It is well known that the subthreshold regime depends on both deep interface trap states and deep bulk trap states so that N trap as calculated above contains contributions from bulk trap states which in turn is likely the reason for the fluctuations of these numbers, e.g., in the case of N2200 (Table S1, Supporting Information).…”

Insight into conduction band density of states at c-Si/TiO2 interface for efficient heterojunction solar cell

“…The effect of silicon crystal orientation on effective mass is also theoretically calculated and put forth by them. Paul et al has demonstrated variation in E c with change in thickness of Si material [69]. They have even demonstrated variation in E c with change in orientation of Si crystal.…”

Electrical characteristic fluctuation of 16-nm-gate high-κ/metal gate bulk FinFET devices in the presence of random interface traps

“…Except planar MOSFETs, fin-type field effect transistors (FinFETs) with HKMG play a key role in sub-22-nm technology nodes to boost electrical performance [ 14 - 16 ] and suppress various fluctuations. Recent studies reported the density of interface traps ( D it ) resulting from the orientations of the vertical fin channel of FinFETs [ 6 , 17 ]. The effects of RITs on sub-22-nm FinFETs have also been reported and compared between different device structures [ 18 , 19 ].…”