Interfacial trap charge and self-heating effect based reliability analysis of a Dual-Drain Vertical Tunnel FET

Das, Diganta; Pandey, Chandan

doi:10.1016/j.microrel.2023.115024

Cited by 15 publications

(1 citation statement)

References 37 publications

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“…Gate-all-around tunnel FETs (GAA-TFETs) 20,21 are expected to exhibit positive impact on the tunneling mechanism owing to reduced screening length (λ), volume inversion across S/C interface due to presence of the surrounding gate which further improves gate controllability over the entire channel. Further, vertical tunnel FET 22,23 structure is the device in which rate of tunneling is improved by activation of the tunneling mechanism is both lateral and vertical directions caused by electric field induced in both the directions around C/S interface. For instance, Madan et al 24 proposed a hetero-dielectric GAA-TFET in which stack of SiO 2 and HfO 2 is used as gate oxide, which improves I ON /I OFF ratio up to 1.2 Â 10 11 .…”

Section: Introductionmentioning

confidence: 99%

GaSb/GaAs Type‐II heterojunction GAA‐TFET with core source for enhanced analog/RF performance and reliability

Karthik,

Pandey

2023

Int J Numerical Modelling

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For the first time, a novel source extension heterojunction gate‐all‐around tunnel FET (SE‐GAA‐TFET) is proposed and examined using Synopsys TCAD simulator in this manuscript. SE‐GAA‐TFET is found to exhibit improved performance in terms of various analog/RF and DC parameters. As channel/source (C/S) interface and electric field exerted by gate are perpendicular to each other, radius of channel is downscaled to enhance electric filed, without reducing area of the tunneling. Furthermore, the presence of GaSb/GaAs heterojunction at C/S interface leads to reduction in the effective band overlap, which helps a great number of mobile charges to tunnel through C/S boundary at ON‐state. The consequences of variation in different geometrical metrics are evaluated to optimize the device performance. SE‐GAA‐TFET is found to offer a current switching ratio (CSR) of ~1013 along with 32.2 mV dec−1 of average sub‐threshold swing (SSAVG). Furthermore, improvement in transconductance and parasitic capacitance boost the cut‐off frequency of SE‐GAA‐TFET up to 37 GHz. Next, both positive and negative traps are introduced at S/C interface and the study reveals that there is no much deviation in parameters of the transfer characteristics like ION, SSAVG, and IOFF of SE‐GAA‐TFET. Next, proper benchmarking is done to compare the performance of the SE‐GAA‐TFET with similar devices available in literature and it is found that proposed SE‐GAA‐TFET exhibits better DC performance due to improved electrostatic behavior. Finally, SE‐GAA‐TFET is found to offer better fall time along with full‐voltage swing when deployed in a resistive load inverter.

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