A novel dual-drain Vertical TFET is proposed and investigated for the first time. The simulation outcomes show that reduction in channel thickness, which has an inadequate impact on tunneling region, significantly improves DC parameters including SSavg, ION, and ION/IOFF by enhancing band-to-band tunneling of charge carriers at source/channel interface caused by enlarged electric field. In order to make proposed device suitable for low power applications, dielectric material is incorporated in between two drain/channel interfaces to reduce leakage current. A detailed investigation is carried out to determine the influence of varying device footprints on various electrical parameters and, accordingly, the optimized device performance is achieved. TCAD-based simulation results reveal that low SSavg of 18mV/decade along with high ION/IOFF of 1.6×〖10〗^13 can be achieved with optimum geometric dimension of gate-oxide, source, and channel. Further, performance of the proposed device is compared with various existing TFET structures and found to be superior in terms of ION/IOFF, SSavg, and turn-on voltage. The probable fabrication process flow is also discussed for a proposed device and based on the proper benchmarking, it is revealed that improvement in parameters defining the switching characteristics of an inverter makes the proposed device more suitable for digital circuit-based applications.

A novel line tunneling based gate-on-source-only tunnel field-effect transistor (TFET) with inverted T-shaped channel (ITGOSO-VTFET) is proposed and investigated using a Synopsis TCAD 2-D simulator. The GOSO configuration along with dual counter-doped pockets (CDP) improve the ON-state current by enhancing the tunneling rate of charge carriers at source/channel interface while inverted T-shaped channel helps the proposed device in reducing the OFF-state (I_OFF) and ambipolar (I_AMB) currents. In comparison with double-gate (DG) and GoSo-CDP TFET, the order of I_OFF (I_AMB) in ITGOSO-VTFET are found to be improved by ~6 (~4) and ~7(~3), respectively. Furthermore, the impact of varying design parameters is analyzed to obtain the optimized performance of the proposed device. Apart from improvement in DC performance, ITGOSO-VTFET is also found to offering a much better analog/radio-frequency performance in terms of various parameters like g_m, f_T, TFP, GBP, and τ, which eventually makes the proposed device more suitable for low power and high-speed applications

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