Interfacing incompatible protocols using interface process generation

Abstract

During system design, one or more p ortions of the system may be implemented with standard c omponents that have a xed pin structure and communication protocol. This paper described a new technique, interface process generation, for interfacing standard c omponents that have incompatible protocols. Given an HDL description of the two protocols, we present a method to generate an interface p r o c ess that allows the two protocols to communicate with each other.

Exploiting intellectual properties in ASIP designs for embedded DSP software

“…We have selected to use the synchronous protocol as our standard one due to the fact that many IP's for DSP applications operate in synchronous (and pipelined) mode. The techniques for the transform have been researched in many works [2][3][4][5][6] and we borrowed one from them, hence we will not go into the subject in detail in this work. The operands in memory are fetched by the in/out-controller and passed to the in-buffer.…”

“…There have been a number of works on the automatic synthesis of interfaces between IP's using different communication protocols [2][3][4][5][6][7]. However, there have not been many works for the efficient use of IP's as accelerators in the processor-core based designs which are common in industries, e.g., ARM-core based designs.…”

Integrating RTL IPs into TLM designs through automatic transactor generation

“…Considering the state of the art, the transactor generation in TLM can be seen as a special case of automatic generation of adapters for incompatible protocols in the RTL context [15,18,3,17]. A technique is presented in [15] for interfacing standard components that have incompatible protocols.…”

“…A technique is presented in [15] for interfacing standard components that have incompatible protocols. Given an RTL HDL description of the two protocols, an interface process is generated to allow the two protocols to communicate with each other.…”

A prototyping platform based on a PCI micronetwork and Leon multiprocessor system

“…Designing SoCs based upon reusable IP cores is essential for meeting stringent time-to-market requirements. Once suitable IP cores are identified, the focus shifts to the integration challenge: how to build a working system from a collection of generic and domain-specific cores that were not designed to work together [7,8]. One of the key issues in hardware/software co-design is thus the generation of suitable interprocess communication interfaces, and to determine the amount and type of communication between different components of a digital system.…”