Abstract-System-level design issues are gaining increasing attention, as behavioral synthesis tools and methodologies mature. We present the SpecSyn system-level design environment, which supports the new specify-explore-refine (SER) design paradigm. This three-step approach to design includes precise specification of system functionality, rapid exploration of numerous systemlevel design options, and refinement of the specification into one reflecting the chosen option. A system-level design option consists of an allocation of system components, such as standard and custom processors, memories, and buses, and a partitioning of functionality among those components. After refinement, the functionality assigned to each component can then be synthesized to hardware or compiled to software. We describe the issues and approaches for each part of the SpecSyn environment. The new paradigm and environment are expected to lead to a more than ten times reduction in design time, and our experiments support this expectation.

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During system design, one or more p ortions of the system may be implemented with standard c omponents that have a xed pin structure and communication protocol. This paper described a new technique, interface process generation, for interfacing standard c omponents that have incompatible protocols. Given an HDL description of the two protocols, we present a method to generate an interface p r o c ess that allows the two protocols to communicate with each other.

When estimating a hardware implementation from behavioral descriptions, an important decision is the selection of a clock cycle to schedule the datapath operations into control steps. Prior to scheduling, most existing behavioral synthesis systems either require the designer to specify the clock cycle explicitly or require that the delays of the operators used in the design be Specified in multiples of a clock cycle. A bad choice of the clock cycle could adversely aflect the performance of the synthesized design. We present an algorithm for estimating the system clock based on a clock slack minimization criteria. The results obtained demonstrate that the clock cycle estimated by the Clock Slack Minimization method produces faster designs than previous solutions to the problem.