Interleaved PWM with discontinuous space-vector modulation

Abstract

This paper describes the effect of interleaved discontinuous space-vector modulation (SVM) in paralleled threephase systems using three-phase pulsewidth modulation (PWM) rectifiers as an example. At the discontinuous point of the SVM, the phase shift between the switching signals of the paralleled modules generates a zero-sequence excitation to the system. Because the conventional control in a balanced three-phase system with only dq channels cannot reject this disturbance, a beatfrequency circulating current will develop on the zero axis. Based on this observation, a SVM without using zero vectors is used to eliminate the cause of pure zero-sequence current for parallel operation. Using this SVM, the circulating current is observable in dq channels. It can be suppressed dynamically by strong current loops of power-factor-correction (PFC) circuits. The concept is verified experimentally on a breadboard system. Index Terms-Circulating current, discontinuous space-vector modulation, interleaved PWM, parallel three-phase system, power electronics building blocks (PEBB's), zero-axis current. I. INTRODUCTION P ARALLEL three-phase power converters/inverters have many advantages, such as higher current capability, less current/voltage ripple, and higher system bandwidth. Previous research exists in applications of UPS, motor drive, and power factor improvements [1]-[6]. As insulated gate bipolar transistors (IGBT's) and other power semiconductor devices are being integrated with gate drives and control intelligence as standardized modules, such as integrated power module (IPM), it becomes quite natural to parallel directly more of these modules together, either to increase the power level and boost the current capability or to design a system with a higher redundancy. Putting modules in parallel, however, is not risk free. One of the major concerns for the parallel operation of a three-phase system is the crosscoupling between modules because when these modules are connected to the same dc bus and a common source/load, extra current conduction paths are formed. Traditionally, in order to avoid this problem, transformers are used to isolate the direct current flow. These transformers are designed with a certain winding turns-ratio and a certain phase shift, so that the concerned harmonics can be canceled in the other side [3], [7]. However, the transformer Manuscript

Space‐vector‐based hybrid PWM for reduced line current ripple and common mode voltage in paralleled interleaved three‐phase two‐level converter

“…Parallel interleaved three-phase inverters form a popular topology in many different applications, such as large drives, high power renewable energy generation and uninterruptable power supplies. The paralleled interleaved three-phase converters share a common DC-link capacitor and the bridge outputs of the inverter are connected via common-mode (CM) inductors, which improve the flexibility and redundancy of the systems [1][2][3][4][5][6][7][8][9][10].…”

“…The decentralised system has two independent controllers, where the primary issue is the asynchronous carriers of two controllers and the research focus on control strategies to synchronise the two carriers [1][2][3]. The centralised architecture does not suffer from asynchronous carriers, and research [4][5][6][7][8][9][10] focusses on the optimisation of vector sequences for key indicators, such as line-current ripple, ZSCC and CMV.…”

“…The maximum ZSCC peak I cirmax determines the size of the CM inductor, and to improve the power density of two parallel interleaved converters, it is essential to suppress the maximum ZSCC peak. Research works of [4][5][6][7][8][9] focus on the suppression of the maximum ZSCC peak, reducing the CM inductor size.…”

“…Reference [4] interleaves the carriers of the two parallel converters and modulates each converter using conventional space vector modulation. However, the consequent interleaved space vector modulation (ISVM) applies the zero vector combinations V 111 -V 000 , causing the largest I cirmax and requiring the larger CM inductor than those of others [5][6][7][8][9]. References [5,6] apply the two-level discontinuous PWM (DPWM) scheme under the interleaved carriers and the consequent interleaved DPWM (IDPWM) eliminates zero vector combinations V 111 -V 000 , reducing the maximum ZSCC peak of ISVM.…”

“…However, the consequent interleaved space vector modulation (ISVM) applies the zero vector combinations V 111 -V 000 , causing the largest I cirmax and requiring the larger CM inductor than those of others [5][6][7][8][9]. References [5,6] apply the two-level discontinuous PWM (DPWM) scheme under the interleaved carriers and the consequent interleaved DPWM (IDPWM) eliminates zero vector combinations V 111 -V 000 , reducing the maximum ZSCC peak of ISVM. Reference [7] investigates the instantaneous CMV difference of IDPWM and concludes that except combinations V 000 -V 000 and V 111 -V 111 , any combinations formed by V 111 or V 000 should be removed.…”