Internal Field Emission at Narrow Silicon and Germanium<mml:math xmlns:mml="http://www.w3.org/1998/Math/MathML" display="inline"><mml:mi>p</mml:mi><mml:mo>−</mml:mo><mml:mi>n</mml:mi></mml:math>Junctions

Chynoweth, A. G.; Feldmann, W. L.; Lee, C. A.; Logan, R. A.; Pearson, G. L.; Aigrain, P.

doi:10.1103/physrev.118.425

Cited by 127 publications

(34 citation statements)

References 9 publications

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“…Junction-tunneling current density as a function of peak electric field in the junction. The filled trian gles are from alloy tunnel diodes, which were reported as step junctions by Chynoweth et al (16]. The filled circles are from diffused emitt er-base junctions repor ted as graded junctions by Fair and \· \Tivell [19).…”

Section: Io·' 10°mentioning

confidence: 99%

“…The junction-tunneling current density Ji is critically dependent on the substrate acceptor concentration n, which must be increased to avoid punch-through as device dimensions are decreased [16][17][18][19][20][21][22]. The scaling law used in this study is plotted in Figure 9.6: (9.10) Given the doping density n, we can compute the depletion-layer thickness x for any potential ' l/J relative to substr ate using the usual step-j unction approximation: x= ~ y---g;;- .…”

Section: Io·' 10°mentioning

confidence: 99%

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Scaling of MOS technology to submicrometer feature sizes

Mead

1994

Analog Integr Circ Sig Process

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Industries based on MOS technology now play a prominent role in t he developed and the developing world. j\fore importantly, MOS techn ology drives a large proportion of innovation in many technologies . It is likely th at the course of technological development depends more on the capability of MOS technology than on any other technical factor . T herefore, it is worthwhile investigating the na.ture and limits of future improvements to MOS fabrication. The key to improved MOS technology is r eduction in feature size. Reduction in feature size, and the attendant changes in device behaviour, will shape the nature of effective uses of the technology at t he system level. This paper reviews recent, and historical, data on feature scaling and device behavior, and attempts to predict the limits to this scaling. We conclude wi th som e remarks on the system-level implications of fea.ture size as the minimum size approach es physical limits. IntroductionIt is always difficult . to nredict the future; few attemp ts to do so have met with resounding su ccess. One remarkable example of successful prediction is the exponential increase in complexity of integrated circuits, first noted by Gordon E . !vioor e. As we contemplate the ongoing evolution of this great technology, many questions arise: Can the trend continue? Will single-chip systems attain levels of complexity that render present system archit ectures unworkable [lj? vVill digital t.echniques completely replace analog methods [2]"7 The answers to these questions depend critically on the properties of the individual transistor s that provide the essential active functions, without which no interesting system beh avior is possible. Integrated-circuit density is increased by a reduction in the size of elementary feat.ures of the underlying structures; therefore, any discussion of the capabilities of future technologies must rely on an understanding of how the properties of transistors evolve as the transistor s' dimensions are made smaller.Elsewhere [3], we described the factors that limit how small an MOS transistor *Reproduced from Journal of VLSI Signal P rocessing, 8 , 9-25 (1994) Kluwer Academic Publishers, Boston. ~fanufacture d in The Netherlands.

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Section: Io·' 10°mentioning

confidence: 99%

Section: Io·' 10°mentioning

confidence: 99%

Scaling of MOS technology to submicrometer feature sizes

Mead

1994

Analog Integr Circ Sig Process

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“…As pointed out by Chynoweth et al [28] and Moll [29] for junctions with breakdown at voltages less than 8 V for GaAs, the mechanism is mainly by tunneling, or direct ®eld ionization of carriers. This breakdown voltage characteristics of Si-doped n-type GaAs is the extension of the V BD at higher dopant concentrations.…”

Section: Resultsmentioning

confidence: 99%

Breakdown characteristics of MOVPE grown Si-doped GaAs Schottky diodes

Hudait

Krupanidhi

1999

Solid-State Electronics

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The breakdown characteristics of Au/n-GaAs Schottky contacts on metal-organic vapor-phase epitaxy grown Sidoped n-GaAs were measured in the doping range of 6 Â 10 15 ±1.5 Â 10 18 cm À3 . These results are compared with the experimentally measured breakdown voltages by several workers and also with the theoretical calculation predicted by Sze and Gibbons [Sze SM, Gibbons G. Appl. Phys. Lett. 1966;8:111]. Good agreement was observed between the measured data and the breakdown voltages by Sze and Gibbons in the high doping concentrations. The maximum depletion layer width is found to be in good agreement with the theoretical analysis by Sze and Gibbons. The breakdown voltage at higher doping concentration will be useful for the design and development of GaAs switching devices and the emitter-base region of bipolar transistors. #

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“…The variable u is associated to the energy of the carriers after tunneling, and m* is the tunneling mass. The m* values for silicon and germanium are typically taken as 0.36 and 0.19 m 0 , respectively, 13 where m 0 is the electron rest mass. It is important to note that the electric field enhancement factor C Dirac decreases exponentially with increasing temperature 11 and is strongly dependent on the parameter values implemented in the model such as the effective mass m* and trap level position.…”

Section: Resultsmentioning

confidence: 99%

Analysis of the Temperature Dependence of Trap-Assisted Tunneling in Ge pFET Junctions

González

Eneman

Wang

et al. 2011

J. Electrochem. Soc.

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In this work, the temperature behavior of trap-assisted tunneling (TAT) in Ge pFET junctions selectively grown in STI substrates is evaluated, whereby the impact of the electric field and the threading dislocation density (TDD) is studied for temperatures ranging from 233 to 418 K. The experimental results are compared with the TAT model for Si proposed by [G. A. M. Hurkx, D. B. M. Klaassen, and M. P. G. Knuvers, IEEE Trans. Electron Devices, 39, 331 (1992)], where several parameters (such as the effective mass and trap level values) are adapted in order to obtain the best agreement between the model and the experimental results. In the frame of channel engineering, Ge pMOS devices are currently being investigated as a potential candidate to extend the technology roadmap below the 22 nm node. This is motivated as follows. For the most recent technology, the implementation of high-k gate dielectrics, which reduces the low-field mobility due to remote phonon and Coulomb scattering, leads to the necessity of searching for new channel materials to achieve a significant carrier mobility enhancement and higher drive current. This offers an excellent opportunity for other materials than Si. For example, Ge is considered for pFETs and Ge or III-V materials for nFETs. Germanium has a 4.4 times higher bulk hole mobility than silicon. This can enhance the circuit speed, through an increase of the transistor drive current or I ON . However, in order to integrate germanium using silicon process tools, Ge transistors need to be fabricated in thin Ge layers processed on a Si handle or carrier wafer, which raises new concerns. One such issue is the presence of extended defects at the Ge/ Si hetero-interface, owing to the 4% lattice mismatch between Si and Ge, which can significantly degrade the mobility enhancement, thus reducing the on-state current.Furthermore, the presence of defects can increase/aggravate the leakage current in the sub-threshold region or I OFF state leakage, through the drain-to-substrate junction leakage.2 Moreover, one of the key concerns for germanium is the narrow bandgap (0.66 eV) compared to unstrained Si (1.1 eV). For advanced CMOS nodes, where higher halo implantations are used and high electric fields are present, the smaller bandgap can considerably increase the drainsubstrate junction leakage for the shorter channel MOSFETs, through field assisted mechanisms like Trap-Assisted Tunneling (TAT) and Band-To-Band Tunneling (BTBT). The high drain-substrate leakage will increase the off-state current and the power consumption. Therefore, it is important to keep a good defect control with an acceptable current level. For this purpose, a better understanding of the field-assisted leakage current mechanisms occurring in the Ge drain-substrate junction is required. ExperimentalProcessing Details.-The Ge pFET junctions were fabricated on 200 mm diameter (100) n-type Czochralski silicon wafers. Active diode regions were defined by shallow trench isolation (STI) followed by P implantations and an n-well anne...

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Internal Field Emission at Narrow Silicon and Germaniump−nJunctions

Cited by 127 publications

References 9 publications

Scaling of MOS technology to submicrometer feature sizes

Scaling of MOS technology to submicrometer feature sizes

Breakdown characteristics of MOVPE grown Si-doped GaAs Schottky diodes

Analysis of the Temperature Dependence of Trap-Assisted Tunneling in Ge pFET Junctions

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