Internode: internal node logic computational model

Millan, A.; Bellido, M.J.; Juan, J.; Guerrero, D.; Ruiz-De-Clavijo, P.; Ostua, E.

doi:10.1109/simsym.2003.1192819

Cited by 3 publications

(3 citation statements)

References 11 publications

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“…On the other hand, leakage power is no longer negligible in current technologies and is being extensively studied by the scientific community [5]. However, only partial progress has been made in modeling and estimating internal power consumption by proposing approximate statistical analyses [6] or generalist behavioral models for the internal states of the gate [7], and no quantitative analysis has yet been found to demonstrate the relevance of this internal power consumption with respect to the total power consumption of a gate.…”

Section: Introductionmentioning

confidence: 99%

Power Dissipation Associated to Internal Effect Transitions in Static CMOS Gates

Millan

Juan

Bellido

et al. 2009

Lecture Notes in Computer Science

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Abstract. Power modeling techniques have traditionally neglected the main part of the energy consumed in the internal nodes of static CMOS gates: the power dissipated by input transitions that do not produce output switching. In this work, we present an experimental set-up that shows that this power component may contribute up to 59% of the total power consumption of a gate in modern technologies. This fact makes very important to include it into any accurate power model. 1

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Section: Introductionmentioning

confidence: 99%

Power Dissipation Associated to Internal Effect Transitions in Static CMOS Gates

Millan

Juan

Bellido

et al. 2009

Lecture Notes in Computer Science

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“…Nevertheless, it is necessary to develop a methodology that allows to reflect this aspect in a comprehensive and methodical way. In this way, we present a new model (called Internode, internal node logic computational model [5]) which is based on a finite state machine (FSM) that represents the internal state of the gate depending on the electrical load of its internal nodes. Such model allows to consider aspects unachievable from traditional models like input collisions and internal power consumption, among others.…”

Section: Introductionmentioning

confidence: 99%

Application of Internode Model to Global Power Consumption Estimation in SCMOS Gates

Calderón

Díaz

Juan-Chico

et al. 2005

Lecture Notes in Computer Science

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Abstract. In this paper, we present a model, Internode, that unifies the gate functional behavior and the dynamic one. It is based on a FSM that represents the internal state of the gate depending on the electrical load of its internal nodes allowing to consider aspects like input collisions and internal power consumption. Also, we explain the importance of internal power consumption (such effect occurs when an input transition does not affect the output) in three different technologies (AMS 0.6 µm, AMS 0.35 µm, and UMC 130 nm). This consumption becomes more remarkable as technology advances yielding to underestimating up to 9.4% of global power consumption in the UMC 130 nm case. Finally, we show how to optimize power estimation in the SCMOS NOR-2 gate by applying Internode to modeling its consumption accurately. 1

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“…Nevertheless, it is necessary to develop a methodology that allows to reflect this aspect in a comprehensive and methodical way. The proposed model (called Internode, Internal node logic computational model [6]) is based on a finite state machine that represents the internal state of the gate depending on the electrical load of its internal nodes (Fig. 1).…”

Section: Functional and Dynamic Behaviors Unificationmentioning

confidence: 99%

Optimization techniques for dynamic behavior modeling of digital CMOS VLSI circuits in nanometric technologies

Millan¹,

Bellido²,

Juan³

Research in Microelectronics and Electronics, 2005 PhD

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In the field of logic simulation, the constant advance of technology influences remarkably in the circuits dynamic behavior. Our main aim is to increase precision of logic simulators by taking into account this influence. This task has two main objectives: (a) developing a model for logic gates that unifies the functional behavior and the dynamic one and (b) developing techniques that improve the characterization processes by using accurate and feasible characterization methods to reduce the error introduced during parameters extraction. The first task has yielded to develop the Internode model, what is based on a finite state machine that represents the internal state of the gate depending on the electrical local of its internal nodes. Such model allows simulators to take into account all the power consumption cases (not only the usually considered ones). On the second task, we have developed a characterization technique based on the use of sampled signals. This technique has improved measurement precision by 5%-8% in the SCMOS inverter case (350 nm technology).

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Internode: internal node logic computational model

Abstract: In this work, we present a computational behavioral model for logic gates called Internode (Internal Node Logic Computational Model)

Cited by 3 publications

References 11 publications

Power Dissipation Associated to Internal Effect Transitions in Static CMOS Gates

Power Dissipation Associated to Internal Effect Transitions in Static CMOS Gates

Application of Internode Model to Global Power Consumption Estimation in SCMOS Gates

Optimization techniques for dynamic behavior modeling of digital CMOS VLSI circuits in nanometric technologies

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