Interplay of voltage and temperature acceleration of oxide breakdown for ultra-thin gate oxides

Wu, Ernest Y.; Suñé, J.; Lai, W.; Nowak, E.; McKenna, J.; Vayshenker, A.; Harmon, D. L.

doi:10.1016/s0038-1101(02)00151-x

Cited by 106 publications

(29 citation statements)

References 25 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…2,21 Taking into account the uncertainties in the linear fits, the extracted  has a weak temperature dependence, indicating that a common trap generation mechanism remains active from room temperature to 120 ˚C. This is consistent with distributions of tBD for both silicon oxide [20][21][22] and AlGaN 2 on each of a series of devices in the same temperature range. Moreover,  obtained here is comparable to that (0.55 − 0.76) for AlGaN/GaN-on-Si HEMTs, 2 suggesting a similar failure mode in the two cases.…”

supporting

confidence: 75%

“…They were distributed along the entire gate finger in a nearly uniform pattern, and were sufficiently far apart to be individually distinguished. As widely used in silicon MOSFETs [19][20][21][22] and lately adopted in GaN-based materials, 2,6 the time-to-breakdown (tBD) for gate degradation can be described by Weibull statistics in which the failure rate is proportional to a power of time. Instead of recording tBD on a series of devices, we monitor the continuous emergence of EL spots at the gate edge on a single device and treat each EL spot as an independent failure site.…”

mentioning

confidence: 99%

See 1 more Smart Citation

Progressive failure site generation in AlGaN/GaN high electron mobility transistors under OFF-state stress: Weibull statistics and temperature dependence

Sun

Bajo

Uren

et al. 2015

Applied Physics Letters

View full text Add to dashboard Cite

Gate leakage degradation of AlGaN/GaN high electron mobility transistors under OFF-state stress is investigated using a combination of electrical, optical, and surface morphology characterizations. The generation of leakage “hot spots” at the edge of the gate is found to be strongly temperature accelerated. The time for the formation of each failure site follows a Weibull distribution with a shape parameter in the range of 0.7–0.9 from room temperature up to 120 °C. The average leakage per failure site is only weakly temperature dependent. The stress-induced structural degradation at the leakage sites exhibits a temperature dependence in the surface morphology, which is consistent with a surface defect generation process involving temperature-associated changes in the breakdown sites.

show abstract

supporting

confidence: 75%

mentioning

confidence: 99%

Progressive failure site generation in AlGaN/GaN high electron mobility transistors under OFF-state stress: Weibull statistics and temperature dependence

Sun

Bajo

Uren

et al. 2015

Applied Physics Letters

View full text Add to dashboard Cite

show abstract

“…To quantify the MTTF of devices undergoing OBD, this work uses the empirical model described in [33], which is based on experimental data collected at IBM [39]. This model is presented in Equation 2.…”

Section: Power Temperature and Mttf Calculationsmentioning

confidence: 99%

Self-calibrating Online Wearout Detection

Blome

Feng

Gupta

et al. 2007

40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO 2007)

View full text Add to dashboard Cite

Technology scaling, characterized by decreasing feature size, thinning gate oxide, and non-ideal voltage scaling, will become a major hindrance to microprocessor reliability in future technology generations. Physical analysis of device failure mechanisms has shown that most wearout mechanisms projected to plague future technology generations are progressive, meaning that the circuit-level effects of wearout develop and intensify with age over the lifetime of the chip. This work leverages the progression of wearout over time in order to present a low-cost hardware structure that identifies increasing propagation delay, which is symptomatic of many forms of wearout, to accurately forecast the failure of microarchitectural structures. To motivate the use of this predictive technique, an HSPICE analysis of the effects of one particular failure mechanism, gate oxide breakdown, on gates from a standard cell library characterized for a 90 nm process is presented. This gate-level analysis is then used to demonstrate the aggregate change in output delay of high-level structures within a synthesized Verilog model of an embedded microprocessor core. Leveraging this analysis, a selfcalibrating hardware structure for conducting statistical analysis of output delay is presented and its efficacy in predicting the failure of a variety of structures within the microprocessor core is evaluated.

show abstract

“…Since all transistors in the adder have the same length, only their width and inputs must be considered. How to weight the different factors is still an open research topic [1][2][20] [22]. However, our empirical results as well as the literature [10] show much higher dependency on the input than on the size of the transistor.…”

Section: How To Identify the Required Fusementioning

confidence: 72%