Interpolating by a factor of 3 in low-voltage low-power ΣΔ DAC

Pracný, Peter; Jørgensen, Ivan Harald Holger; Bruun, Erik

doi:10.1007/s10470-014-0327-8

Cited by 2 publications

(3 citation statements)

References 12 publications

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“…Hence, a figure of merit (FOM) developed for digital filters [2, 28,35] can be applied. In this work, the FOM is used to judge the complexity of the IF and the  modulator by counting the number and complexity of adders [11,[20][21][22][23]. This leads to…”

Section: Design Specifications and Figure-of-meritmentioning

confidence: 99%

“…The only block of the DAC that remains to be investigated is the  modulator. This has been done in [22][23], and the investigation shows that in order to achieve the necessary performance of SQNR and MSA, the maximum gain of NTF, Hinf, of the  modulator must be increased significantly above the recommendations in [27].…”

Section: Using Interpolation Factor Ofmentioning

confidence: 99%

“…In order to achieve OSR = 24, one of the stages of the IF has to perform sample rate increase by a factor of 3. In [22][23], two cases are investigated. Table 4.…”

Section: Using Interpolation Factor Ofmentioning

confidence: 99%

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System-Level Power Optimization of Digital Audio Back End for Hearing Aids

Pracný¹,

Jørgensen

Bruun

2016

Circuits Syst Signal Process

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Abstract:Abstract-This work deals with power optimization of the audio processing back end for hearing aids -the interpolation filter (IF), the sigma-delta (SD modulator and the Class D power amplifier (PA) as a whole. Specifications are derived and insight into the tradeoffs involved is used to optimize the interpolation filter and the SD modulator on the system level so that the switching frequency of the Class D PA -the main power consumer in the back end -is minimized. A figure-of-merit (FOM) which allows judging the power consumption of the digital part of the back end early in the design process is used to track the hardware and power demands as the tradeoffs of the system level parameters are investigated. The result is the digital part of the back end optimized with respect to power which provides audio performance comparable to state-of-theart. A combination of system level parameters leading to the lowest switching frequency of the Class D power amplifier reported in literature for the SD modulatorbased back end is derived using this approach. Response to Reviewers:This submission is the final version of our manuscript. According to the instructions for authors and the email from the editor the following changes were done: -the order of the refernces was changed to alphabetic order.-footnote with contact information of all authors was added on the first page Thank you. Powered by Editorial Manager® and ProduXion Manager® from Aries Systems CorporationPeter Pracný, Abstract-This work deals with power optimization of the audio processing back end for hearing aids -the interpolation filter (IF), the sigma-delta ( modulator and the Class D power amplifier (PA) as a whole. Specifications are derived and insight into the tradeoffs involved is used to optimize the interpolation filter and the  modulator on the system level so that the switching frequency of the Class D PA -the main power consumer in the back end -is minimized. A figure-of-merit (FOM) which allows judging the power consumption of the digital part of the back end early in the design process is used to track the hardware and power demands as the tradeoffs of the system level parameters are investigated. The result is the digital part of the back end optimized with respect to power which provides audio performance comparable to state-of-the-art. A combination of system level parameters leading to the lowest switching frequency of the Class D power amplifier reported in literature for the  modulator-based back end is derived using this approach.

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