Interval simulation: Raising the level of abstraction in architectural simulation

Genbrugge, Davy; Eyerman, Stijn; Eeckhout, Lieven

doi:10.1109/hpca.2010.5416636

Cited by 104 publications

(74 citation statements)

References 37 publications

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“…An additional advantage of interval simulation is that the instructions (or micro-ops) are held and processed just one time and in program order. This simulation technique allows for speedups of more than 10× when compared to M5 [Binkert et al 2006], with an average error of 4.6% [Genbrugge et al 2010].…”

Section: Interval Simulationmentioning

confidence: 99%

“…Interval simulation [Genbrugge et al 2010] is an extension of the interval model to allow for the simulation of multicore processors using the insights of the interval model. The major advantage of interval simulation over interval modeling is the ability to simulate multicore platforms.…”

Section: Interval Simulationmentioning

confidence: 99%

“…We first provide an overview of interval simulation [Genbrugge et al 2010], a high-level mechanistic core model that produces fast and accurate simulation results. We present improvements that build on interval simulation as well as extend it in a new direction for higher simulation accuracy.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

An Evaluation of High-Level Mechanistic Core Models

Carlson

Heirman²,

Eyerman

et al. 2014

ACM Trans. Archit. Code Optim.

Self Cite

280

136

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Large core counts and complex cache hierarchies are increasing the burden placed on commonly used simulation and modeling techniques. Although analytical models provide fast results, they do not apply to complex, many-core shared-memory systems. In contrast, detailed cycle-level simulation can be accurate but also tends to be slow, which limits the number of configurations that can be evaluated. A middle ground is needed that provides for fast simulation of complex many-core processors while still providing accurate results.In this article, we explore, analyze, and compare the accuracy and simulation speed of high-abstraction core models as a potential solution to slow cycle-level simulation. We describe a number of enhancements to interval simulation to improve its accuracy while maintaining simulation speed. In addition, we introduce the instruction-window centric (IW-centric) core model, a new mechanistic core model that bridges the gap between interval simulation and cycle-accurate simulation by enabling high-speed simulations with higher levels of detail. We also show that using accurate core models like these are important for memory subsystem studies, and that simple, naive models, like a one-IPC core model, can lead to misleading and incorrect results and conclusions in practical design studies. Validation against real hardware shows good accuracy, with an average single-core error of 11.1% and a maximum of 18.8% for the IW-centric model with a 1.5× slowdown compared to interval simulation.

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Section: Interval Simulationmentioning

confidence: 99%

Section: Interval Simulationmentioning

confidence: 99%

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An Evaluation of High-Level Mechanistic Core Models

Carlson

Heirman²,

Eyerman

et al. 2014

ACM Trans. Archit. Code Optim.

Self Cite

280

136

View full text Add to dashboard Cite

show abstract

“…Simulation results presented in this study use Sniper's interval core model, which is significantly faster to simulate than detailed core models found in other academic simulators [11]. In addition, its memory model is relatively complex as it supports shared caches in a parallelized simulation platform.…”

Section: E Potential For Simulator Speedupmentioning

confidence: 99%

Sampled simulation of multi-threaded applications

Carlson

Heirman

Eeckhout

2013

2013 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)

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Abstract-Sampling is a well-known workload reduction technique that allows one to speed up architectural simulation while accurately predicting performance. Previous sampling methods have been shown to accurately predict single-threaded application runtime based on its overall IPC. However, these previous approaches are unsuitable for general multi-threaded applications, for which IPC is not a good proxy for runtime. Additionally, we find that issues such as application periodicity and inter-thread synchronization play a significant role in determining how best to sample these applications.The proposed multi-threaded application sampling methodology is able to derive an effective sampling strategy for candidate applications using architecture-independent metrics. Using this methodology, large input sets can now be simulated which would otherwise be infeasible, allowing for more accurate conclusions to be made than from studies using scaled-down input sets. Through the use of the proposed methodology, we can simulate less than 10% of the total application runtime in detail. On the SPEComp, NPB and PARSEC benchmarks, running on an 8-core simulated system, we achieve an average absolute error of 3.5%.

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“…Instead of modelling micro-architectural structures within the CPU, it employs the mechanistic Interval Simulation model [26]. The higher level of abstraction of interval simulation is directly reflected in a higher simulation speed, compared to more detailed models.…”

Section: Related Workmentioning

confidence: 99%

TaskPoint: Sampled simulation of task-based programs

Grass

Rico

Casas

et al. 2016

2016 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)

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Abstract-Sampled simulation is a mature technique for reducing simulation time of single-threaded programs, but it is not directly applicable to simulation of multi-threaded architectures. Recent multi-threaded sampling techniques assume that the workload assigned to each thread does not change across multiple executions of a program. This assumption does not hold for dynamically scheduled task-based programming models. Taskbased programming models allow the programmer to specify program segments as tasks which are instantiated many times and scheduled dynamically to available threads. Due to system noise and variation in scheduling decisions, two consecutive executions on the same machine typically result in different instruction streams processed by each thread.In this paper, we propose TaskPoint, a sampled simulation technique for dynamically scheduled task-based programs. We leverage task instances as sampling units and simulate only a fraction of all task instances in detail. Between detailed simulation intervals we employ a novel fast-forward mechanism for dynamically scheduled programs. We evaluate the proposed technique on a set of 19 task-based parallel benchmarks and two different architectures. Compared to detailed simulation, TaskPoint accelerates architectural simulation with 64 simulated threads by an average factor of 19.1 at an average error of 1.8% and a maximum error of 15.0%.

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Interval simulation: Raising the level of abstraction in architectural simulation

Cited by 104 publications

References 37 publications

An Evaluation of High-Level Mechanistic Core Models

An Evaluation of High-Level Mechanistic Core Models

Sampled simulation of multi-threaded applications

TaskPoint: Sampled simulation of task-based programs

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