“…Several on-chip antennas are proposed by Kenneth et al in [85][86][87][88][89][90][91][92]. With respect to these designs, the bow-tie antenna proposed in this work stands out for its large bandwidth, which is an added value of the selected bow-tie approach.…”
Section: Comparison Of the Designed Antenna Vs The State-of-the-artmentioning
confidence: 99%
“…[31,37,40,67,69,[75][76][77][78][79][80][81][82][83][84][85][86][87][88][89][90][91][92][93][94]. Specifically, Table 2 compares the proposed design to [31,37,40,67,79,83] in terms of area, gain, HPBW and bandwidth.…”
Section: Comparison Of the Designed Antenna Vs The State-of-the-artmentioning
confidence: 99%
“…In Ref. [86], Kenneth et al propose on-chip wireless interconnections for clock signal distribution. In Ref.…”
Section: Comparison Of the Designed Antenna Vs The State-of-the-artmentioning
Abstract:To allow fast communication-at several Gb/s-of multimedia content among processors and memories in a multi-processor system-on-chip, a new approach is emerging in literature: Wireless Network-on-Chip (WiNoC). With reference to this scenario, this paper presents the design of the key element of the WiNoC: the antenna. Specifically, a bow-tie antenna is proposed, which operates at mm-waves and can be implemented on-chip using the top metal layer of a conventional silicon CMOS (Complementary Metal Oxide Semiconductor) technology. The antenna performance is discussed in the paper and is compared to the state-of-the-art, including the zig-zag antenna topology that is typically used in literature as a reference for WiNoC. The proposed bow-tie antenna design for WiNoC stands out for its good trade-off among bandwidth, gain, size and beamwidth vs. the state-of-the-art.
“…Several on-chip antennas are proposed by Kenneth et al in [85][86][87][88][89][90][91][92]. With respect to these designs, the bow-tie antenna proposed in this work stands out for its large bandwidth, which is an added value of the selected bow-tie approach.…”
Section: Comparison Of the Designed Antenna Vs The State-of-the-artmentioning
confidence: 99%
“…[31,37,40,67,69,[75][76][77][78][79][80][81][82][83][84][85][86][87][88][89][90][91][92][93][94]. Specifically, Table 2 compares the proposed design to [31,37,40,67,79,83] in terms of area, gain, HPBW and bandwidth.…”
Section: Comparison Of the Designed Antenna Vs The State-of-the-artmentioning
confidence: 99%
“…In Ref. [86], Kenneth et al propose on-chip wireless interconnections for clock signal distribution. In Ref.…”
Section: Comparison Of the Designed Antenna Vs The State-of-the-artmentioning
Abstract:To allow fast communication-at several Gb/s-of multimedia content among processors and memories in a multi-processor system-on-chip, a new approach is emerging in literature: Wireless Network-on-Chip (WiNoC). With reference to this scenario, this paper presents the design of the key element of the WiNoC: the antenna. Specifically, a bow-tie antenna is proposed, which operates at mm-waves and can be implemented on-chip using the top metal layer of a conventional silicon CMOS (Complementary Metal Oxide Semiconductor) technology. The antenna performance is discussed in the paper and is compared to the state-of-the-art, including the zig-zag antenna topology that is typically used in literature as a reference for WiNoC. The proposed bow-tie antenna design for WiNoC stands out for its good trade-off among bandwidth, gain, size and beamwidth vs. the state-of-the-art.
“…for large (8) Finally, we have to account as well for the capacitance in the buffer at the top of the distribution tree: (9) Note that the buffer capacitance is small and nearly independent of the size of the distribution tree . We can therefore neglect the power consumption of the top buffer.…”
Section: B Modeling Of the Required Electrical Switching Powermentioning
confidence: 99%
“…Indeed, radically different clocking approaches-from novel architectures to alternative signaling media-are being researched in academia. Distributed PLL networks across the chip [7], on-chip wireless clock distribution [8], salphasic clocks [9] and optical clocks are among the most promising approaches.…”
Abstract-We present a new technique of injecting clocks optically onto CMOS chips without the use of a receiver amplifier. We discuss the benefits of such a direct approach and present proof-ofprinciple experiments of the technique. We analytically compare a receiver-less optical clock distribution and an electrical clock distribution in a fan-out-of-four clock tree to evaluate the timing and power benefits of the optical approach for present microprocessors. We also compare receiver-less direct injection of optical clocks to trans-impedance receiver based injection within the same distribution framework.
The design of monolithic antennas for manufacturing using primarily silicon‐based technologies is presented in this article, with emphasis on space‐efficient, low‐gain antennas suitable for integration in active‐device processes. Different micromachining methods for improving the performance of the integrated antennas are considered.
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