Intrinsic shortest path length: a new, accurate a priori wirelength estimator

Kahng, Andrew B.; Reda, Sherief

doi:10.1109/iccad.2005.1560059

Cited by 15 publications

(34 citation statements)

References 25 publications

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“…Brief literature reviews of a priori wirelength estimation works for ASICs and FPGAs can be seen in [2], [6]. Five of the recent works are shown in Table I, where the average estimate errors reported in the corresponding papers are also shown.…”

Section: Introductionmentioning

confidence: 99%

“…If designers know the total wirelength of a design prior to the physical design stages and at the early design stages take proper actions to meet the design requirements, then they can avoid to have to go through the time-consuming physical design stages multiple times. In addition, the design exploration and optimization performed at the early design stages, such as physical synthesis, are more effective in achieving the desired goals [2]- [4].…”

Section: Introductionmentioning

confidence: 99%

“…Therefore, research on a priori wirelength estimation has been carried out in [2], [4]- [7]. In [2], the relationship between the wirelength and the intrinsic shortest path length of nets is identified and used to estimate the total wirelength.…”

Section: Introductionmentioning

confidence: 99%

“…In [2], the relationship between the wirelength and the intrinsic shortest path length of nets is identified and used to estimate the total wirelength. A stochastic wirelength estimation approach is proposed in [4], which estimates the wirelength based on the number of gates, the Rent exponent and the Rent coefficient.…”

Section: Introductionmentioning

confidence: 99%

“…Note that these evaluations are based on different benchmarks. In [2], the intrinsic shortest path length (ISPL) of a two-pin net is defined as the minimum number of edges connecting the two terminals, excluding the direct connecting edge between the two terminals. A correlation coefficient of 0.914, on average, between the wirelength and the ISPL is shown for a set of circuits.…”

Section: Introductionmentioning

confidence: 99%

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Neural network based pre-placement wirelength estimation

Liu

Zhang

2012

2012 International Conference on Field-Programmable Technology

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We propose a neural network based approach for estimating the total wirelength of a digital circuit, mapped onto an FPGA, before circuit placement and routing. A 3-layer MLP neural network is trained to learn the behavior of a placement tool and then quickly predicts the wirelength of a circuit design with the accuracy similar to one obtained after placement. A priori knowledge about the wirelength of circuit designs can be used to effectively guide the design exploration processes at the early design stages. This breaks the repetitive CAD design flow and reduces the design cycle. In this work, five circuit parameters and two FPGA architecture parameters are considered in the wirelength estimation. The proposed approach is evaluated by comparing the wirelength given by the trained neural networks and the placement tool VPR for the IWLS2005 circuit benchmark. Results show that the neural network's estimation has an average error below 0.6% compared to VPR. The neural network model is also compared to a linear model for the wirelength estimation, showing 7.39 times improvement in the estimation accuracy.

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Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Neural network based pre-placement wirelength estimation

Liu

Zhang

2012

2012 International Conference on Field-Programmable Technology

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A pre-placement individual net length estimation model and an application for modern circuits

et al. 2011

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A-priori individual interconnect length estimates can be used to make placement efficient and reduce delay and power consumption in a circuit. However, finding lengths of individual interconnects before their terminals have been placed can be a daunting task. In this thesis, the main characteristics that need to be considered while designing an individual a-priori length estimation technique for today's integrated circuits are discussed. Then, a technique for estimating individual interconnect lengths for mixed-size circuits based on Radial Basis Functions (RBFs) is proposed. The advantage of using RBFs, is that the given data do not need to be fitted into a pre-defined model such as a polynomial. In this thesis, a method is proposed to calculate a suitable variance parameter of the RBFs. An application of the length estimator is proposed where a predictor-corrector framework for clustering that can be used to improve the results of placement is implemented.

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Stochastic wire-length model with TSV placement on periphery area

Ling

et al. 2014

2014 IEEE 16th Electronics Packaging Technology Conference (EPTC)

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Intrinsic shortest path length: a new, accurate a priori wirelength estimator

Cited by 15 publications

References 25 publications

Neural network based pre-placement wirelength estimation

Neural network based pre-placement wirelength estimation

A pre-placement individual net length estimation model and an application for modern circuits

Stochastic wire-length model with TSV placement on periphery area

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