Introducing a Performance Model for Bandwidth-Limited Loop Kernels

Treibig, Jan; Hager, Georg

doi:10.1007/978-3-642-14390-8_64

Cited by 49 publications

(67 citation statements)

References 1 publication

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The consequence is that single core performance is not quantitatively accurate for memory-bound kernels (it is too optimistic). Hence, in particular, multicore scalability can not be inferred from this model [3,8]. Moreover, the GFlop/s metric which is generally used with Roofline models has some drawbacks from a practical methodological point of view.…”

Section: The Roofline Modelmentioning

confidence: 99%

“…The ECM model ( [3], [8]) is a refinement of the Roofline model for multicore CPUs that still neglects any latency effects, but takes into account the cache hierarchy. It uses the cycles per cacheline worth of data (cy/CL) performance metric.…”

Section: The Ecm Modelmentioning

confidence: 99%

“…Hence, similarly to the scientific method applied to physics or engineering, if our performance model is rich enough to adequately capture the behaviour of our algorithm, it can be used not only for quantitative prediction, but also for precise qualitative understanding. In a previous work [2], we established that the so-called ECM model [3] has the capability to accurately predict Lagrange-Remap solver performance on multicore CPUs.…”

Section: Introductionmentioning

confidence: 99%

“…This underlying hardware complexity implies that precisely predicting and understanding the performance of even deceptively simple algorithms such as the Schönauer Vector Triad A = B + C * D (where A, B, C and D are arrays) on a typical multicore CPU is not trivial [3]. However, some successful analytical performance models have been recently popularized in order to assess algorithmic performance on recent hardware.…”

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

Building a More Efficient Lagrange-Remap Scheme Thanks to Performance Modeling

Gasc¹,

Vuyst²,

Peybernes³

et al. 2016

Proceedings of the VII European Congress on Computational Methods in Applied Sciences and Engineering (ECCOMAS Congress 2016)

View full text Add to dashboard Cite

Abstract. This paper is a practical example of co-design between numerical analysis and high performance computing, applied to compressible fluid mechanics. We consider a legacy numerical method, based on a Lagrange-Remap solver for the compressible Euler equations, use tools from analytical performance modeling to quantitatively understand its behavior on recent multicore CPUs, and extract its computational bottlenecks. This analysis inspires us to propose a new numerical method, called Lagrange-Flux. Experimental results show that this new method yields an algorithm that is more computationally efficient, and at the same time retains the good numerical properties of the original Lagrange-Remap solver.

show abstract

Section: The Roofline Modelmentioning

confidence: 99%

Section: The Ecm Modelmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Building a More Efficient Lagrange-Remap Scheme Thanks to Performance Modeling

Gasc¹,

Vuyst²,

Peybernes³

et al. 2016

Proceedings of the VII European Congress on Computational Methods in Applied Sciences and Engineering (ECCOMAS Congress 2016)

View full text Add to dashboard Cite

show abstract

“…The roofline model can predict the performance of a simple von Neumann architecture with two levels of memory as well as the more complex design with a multi-level memory hierarchy. It has been successfully used to model the performance of many applications on the multi-core and many-core processors [22]. Recently, it has been extended to model the energy consumption in GPUs [23].…”

Section: Related Workmentioning

confidence: 99%

Energy aware scheduling model and online heuristics for stencil codes on heterogeneous computing architectures

2016

View full text Add to dashboard Cite

Performance of high-end supercomputers will reach the exascale through the advent of core counts in billions. However, in the upcoming exascale computing era it is important not only to focus on the performance, but also on scalability of fine-grained parallel applications, data locality and energy aware scheduling within the parallel code. In fact, parallel applications need to change even now by redesigning algorithms and data structures respectively to take advantage of the recent improvements in energy efficiency of heterogeneous computing hardware, including multicore processors and GPU accelerators. Over the next few years one of the biggest challenges for exascale will be the ability of parallel applications to fully exploit locality which will, in turn, be required to achieve expected performance and energy efficiency. Future highly parallel applications will have to deal with deep memory hierarchies taking into account energy cost in moving data off-chip. Therefore, they will have to apply new coordinated scheduling approaches to balance energy aware resource utilization and minimize work starvation during runtime. As new constraints and limits on memory bandwidth and energy will play a key role in high performance computing (HPC) in the future, more sophisticated and dynamic scheduling techniques will be needed and applied within the parallel code. In this paper we focus on an energy-aware distribution of the stencil workload on heterogeneous processors. Our analysis of energy and performance models focused on relevant class of stencil computations to explore the relationship between task scheduling algorithms and energy constraints. More precisely, we search for a schedule which minimizes the energy usage within a specified computation's deadline of the stencil workload on heterogeneous architectures. Since the problem is computationally intractable, we present an integer linear programming formulation for finding optimal schedules. As finding optimal schedules is time consuming we have developed four heuristics and tested them experimentally with respect to optimal solutions. In our work we focus on a single node configurations with heterogeneous processors. These configurations represent the state of the art multi-and many-core architectures.

show abstract

Exploring performance and power properties of modern multi‐core chips via simple machine models

Hager¹,

Treibig²,

Habich³

et al. 2013

Concurrency and Computation

Self Cite

115

View full text Add to dashboard Cite

Modern multicore chips show complex behavior with respect to performance and power. Starting with the Intel Sandy Bridge processor, it has become possible to directly measure the power dissipation of a CPU chip and correlate this data with the performance properties of the running code. Going beyond a simple bottleneck analysis, we employ the recently published Execution-Cache-Memory (ECM) model to describe the singleand multi-core performance of streaming kernels. The model refines the well-known roofline model, since it can predict the scaling and the saturation behavior of bandwidth-limited loop kernels on a multicore chip. The saturation point is especially relevant for considerations of energy consumption. From power dissipation measurements of benchmark programs with vastly different requirements to the hardware, we derive a simple, phenomenological power model for the Sandy Bridge processor. Together with the ECM model, we are able to explain many peculiarities in the performance and power behavior of multicore processors, and derive guidelines for energy-efficient execution of parallel programs. Finally, we show that the ECM and power models can be successfully used to describe the scaling and power behavior of a lattice-Boltzmann flow solver code.

show abstract

Introducing a Performance Model for Bandwidth-Limited Loop Kernels

Cited by 49 publications

References 1 publication

Building a More Efficient Lagrange-Remap Scheme Thanks to Performance Modeling

Building a More Efficient Lagrange-Remap Scheme Thanks to Performance Modeling

Energy aware scheduling model and online heuristics for stencil codes on heterogeneous computing architectures

Exploring performance and power properties of modern multi‐core chips via simple machine models

Contact Info

Product

Resources

About