Introducing redundancy in field programmable gate arrays

Hatori, F.; Sakurai, Takayasu; Nogami, K.; Sawada, Katsutoshi; Takahashi, Masafumi; Ichida, M.; Uchida, M.; Yoshii, I.; Kawahara, Y.; Hibi, T.; Saeki, Yukihiro; Muroga, H.; Tanaka, Atsushi; Kanzaki, K.

doi:10.1109/cicc.1993.590575

Cited by 65 publications

(47 citation statements)

References 3 publications

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“…Performance and power consumption are also impacted by this scheme because routing must be made longer to allow connections to span a defective row or column. This has been estimated to only cause a 5% increase to interconnect delays [94] but this has not been reevaluated for recent architectures. One new challenge for this defect tolerance scheme is the heterogeneous blocks that are commonly included in modern FPGAs as they add complexity to these coarse-grained redundancy approaches and, with few exceptions [172], such issues have yet to be examined.…”

Section: Manufacturing Defectsmentioning

confidence: 99%

“…This was first suggested in [94] and was more recently evaluated in [241]. This coarse grain scheme is also used commercially [50,148].…”

Section: Manufacturing Defectsmentioning

confidence: 99%

“…The overhead of this approach includes both the area for the spare rows/columns that are unused in defect-free FPGAs and the additional logic that must be added to enable the shifting. The latter factor was estimated to cause a 2% area increase for an early FPGA architecture [94] while the cost of the spare rows/columns depends on the number of spare rows/columns which is determined by the desired level of defect tolerance. Performance and power consumption are also impacted by this scheme because routing must be made longer to allow connections to span a defective row or column.…”

Section: Manufacturing Defectsmentioning

confidence: 99%

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FPGA Architecture: Survey and Challenges

Kuon

Tessier

Rose

2008

FNT in Electronic Design Automation

330

109

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Field-Programmable Gate Arrays (FPGAs) have become one of the key digital circuit implementation media over the last decade. A crucial part of their creation lies in their architecture, which governs the nature of their programmable logic functionality and their programmable interconnect. FPGA architecture has a dramatic effect on the quality of the final device's speed performance, area efficiency, and power consumption. This survey reviews the historical development of programmable logic devices, the fundamental programming technologies that the programmability is built on, and then describes the basic understandings gleaned from research on architectures. We include a survey of the key elements of modern commercial FPGA architecture, and look toward future trends in the field.

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Section: Manufacturing Defectsmentioning

confidence: 99%

“…This was first suggested in [94] and was more recently evaluated in [241]. This coarse grain scheme is also used commercially [50,148].…”

Section: Manufacturing Defectsmentioning

confidence: 99%

Section: Manufacturing Defectsmentioning

confidence: 99%

See 1 more Smart Citation

FPGA Architecture: Survey and Challenges

Kuon

Tessier

Rose

2008

FNT in Electronic Design Automation

330

109

View full text Add to dashboard Cite

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“…Cheatham et al (2006), a detailed quantitative analysis of various FT methods (both offline and online) are given. Several techniques used either row-wise shifting or column-wise shifting (Hatori et al, 1993;Caponetto et al, 2007). Hatori et al (1993), the authors provided a single spare column technique for fault toleration.…”

Section: Related Researchmentioning

confidence: 99%

“…Several techniques used either row-wise shifting or column-wise shifting (Hatori et al, 1993;Caponetto et al, 2007). Hatori et al (1993), the authors provided a single spare column technique for fault toleration. The authors used specialized selector circuitry, which is useful to reconfigure faulty FPGAs.…”

Section: Related Researchmentioning

confidence: 99%

Reconfiguring Evolved Circuits Using Controller: A Real Time Approach

Krishna¹

2014

Journal of Computer Science

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FPGA is a device that contains a matrix of reconfigurable gate arrays that can implement different complex functions and also vary structurally. In this study, a novel method of reconfigurable circuit switching action is done with the help of a controller. BPSK Modulation application is chosen to demonstrate the reconfigurable action. When an event occurs the context/core switching is done at both input and output and also preserving the structural and functional relationship. The reconfiguration ability of FPGA with an embedded core performing the switching in real time is the focus of this study. A controller running on Linux platform is used along with the FPGA core. In this study, we propose a real time approach for reconfiguring evolved circuits using controller. It has an adaptive hardware that can continuously change in response to the input data and there by perform reconfiguration. Here the reconfiguration process is achieved by using a real time controller which gives a command to the FPGA core (ALTERA (Cypress processor)) for reconfiguration.

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