Introduction to VLSI Silicon Devices

El-Kareh, Badih; Bombard, Richard J.

doi:10.1007/978-1-4613-2275-7

Cited by 26 publications

(10 citation statements)

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“…This indicates that depletion width is increasing and moving towards source with V DS . [33][34][35][36] Inset figure shows the lateral electric field in the lateral direction for highly doped device with N SUB = 10 17 =cm 3 , while all the other parameters remain the same. As seen in the inset figure, V DS does not has significant impact on the drain side depletion width, since the doping is high, so therefore the negative value of electric-field is not significantly large, as compare to the negative value of electric-field for the low channel doping case.…”

Section: Effect Of Drain Voltagementioning

confidence: 99%

“…In simple words, we can say that as the V DS increases, the drain side depletion region moves towards the source side depletion region and for some drain voltage (punch-through voltage) the two regions merge together. 33,34,37) This causes the leakage current to flow from drain to source, and this phenomenon is called punch-through phenomenon.…”

Section: Effect Of Drain Voltagementioning

confidence: 99%

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Analysis and modeling of zero-threshold voltage native devices with industry standard BSIM6 model

Gupta

Agarwal

Lin

et al. 2017

Jpn. J. Appl. Phys.

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In this paper, we present the modeling of zero-threshold voltage (VTH) bulk MOSFET, also called native devices, using enhanced BSIM6 model. Devices under study show abnormally high leakage current in weak inversion, leading to degraded subthreshold slope. The reasons for such abnormal behavior are identified using technology computer-aided design (TCAD) simulations. Since the zero-VTH transistors have quite low doping, the depletion layer from drain may extend upto the source (at some non-zero value of VDS) which leads to punch-through phenomenon. This source–drain leakage current adds with the main channel current, causing the unexpected current characteristics in these devices. TCAD simulations show that, as we increase the channel length (Leff) and channel doping (NSUB), the source–drain leakage due to punch-through decreases. We propose a model to capture the source–drain leakage in these devices. The model incorporates gate, drain, body biases and channel length as well as channel doping dependency too. The proposed model is validated with the measured data of production level device over various conditions of biases and channel lengths.

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Section: Effect Of Drain Voltagementioning

confidence: 99%

Section: Effect Of Drain Voltagementioning

confidence: 99%

Analysis and modeling of zero-threshold voltage native devices with industry standard BSIM6 model

Gupta

Agarwal

Lin

et al. 2017

Jpn. J. Appl. Phys.

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“…The dependence of subthreshold current on a gate bias is expressed as follows [14]: (1) where is flat-band voltage and is the slope of the subthreshold current. The relationship between and temperature is approximated by [14] (2)…”

Section: Modeling Of a Subthreshold Current Transientmentioning

confidence: 99%

Characterization of various stress-induced oxide traps in MOSFET's by using a subthreshold transient current technique

Wang

Chiang²,

Zous³

et al. 1998

IEEE Trans. Electron Devices

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“…While the neutrality is broken, we should introduce Poisson equation. For details, we refer to [1][2][3][4] and the references therein. The model is a nonlinear system of elliptic equations.…”

Section: Introductionmentioning

confidence: 99%