Inventory of silicon signatures induced by CDM event on deep sub-micronic CMOS–BICMOS technologies

Investigation on CDM ESD events at core circuits in a 65-nm CMOS process

“…The typical 1-kV CDM ESD event from a charged IC (with an equivalent 4-pF capacitance to ground) can generate a current peak as high as $15 A within a rise time of only $0.2 ns [8]. Among the chip-level ESD test standards, the CDM ESD events play major roles to cause failures in today's manufacturing and packaging environments [9,10]. Therefore, several ESD protection designs against CDM ESD events have been reported to protect the I/O circuits which are directly connected to the external pins [11][12][13].…”