Inverter delay modelling for submicrometre CMOSprocess

Daga, J.M.; Turgis, S.; Auvergne, D.

doi:10.1049/el:19961394

Cited by 12 publications

(1 citation statement)

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“…Previous work, such as e.g. [2], [3], [4], [5], and [6] have given approximations to the propagation delay of an inverter at low input frequencies with no regard for PSN. This work is part of a larger effort to characterize the different building blocks of CGCs to give a designer means of comparing which architecture is least sensitive to PSN from a jitter stand-point.…”

Section: Introductionmentioning

confidence: 99%

Analysis of timing jitter in inverters induced by power-supply noise

Strak

Tenhunen

2006

International Conference on Design and Test of Integrated Systems in Nanoscale Technology, 2006. DTIS 2006.

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This paper describes the transformation process of power-supply noise (PSN) to timing jitter of inverters. The focus is on the inverters used in multiphase clock-generator circuits (CGCs) commonly needed for Switched-Capacitor (SC) Sigma-Delta (ΣΔ) Analog-to-Digital Converters (ADCs). Closed form expressions relating timing jitter and PSN are presented and the results are compared with Monte-Carlo simulations performed in Spectre at BSIM3v3 transistor model level using the processes AMS 0.35µm and UMC 0.18µm. The PSN is assumed to have a white frequency distribution with independent power and ground noise. The results show that the transformation process is approximately linear and that the jitter impact decreases as transistors move deeper into the submicron domain. Furthermore, the transformation process is not symmetrical and is dependent on switching direction, even if the PMOS and NMOS sizings are such that the effects due to difference in hole and electron mobility are mitigated.

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