Investigate on the Mechanism of HfO2/Si0.7Ge0.3 Interface Passivation Based on Low-Temperature Ozone Oxidation and Si-Cap Methods

Abstract

The interface passivation of the HfO2/Si0.7Ge0.3 stack is systematically investigated based on low-temperature ozone oxidation and Si-cap methods. Compared with the Al2O3/Si0.7Ge0.3 stack, the dispersive feature and interface state density (Dit) of the HfO2/Si0.7Ge0.3 stack MOS (Metal-Oxide-Semiconductor) capacitor under ozone direct oxidation (pre-O sample) increases obviously. This is because the tiny amounts of GeOx in the formed interlayer (IL) oxide layer are more likely to diffuse into HfO2 and cause the HfO2/Si0.7Ge0.3 interface to deteriorate. Moreover, a post-HfO2-deposition (post-O) ozone indirect oxidation is proposed for the HfO2/Si0.7Ge0.3 stack; it is found that compared with pre-O sample, the Dit of the post-O sample decreases by about 50% due to less GeOx available in the IL layer. This is because the amount of oxygen atoms reaching the interface of HfO2/Si0.7Ge0.3 decreases and the thickness of IL in the post-O sample also decreases. To further reduce the Dit of the HfO2/Si0.7Ge0.3 interface, a Si-cap passivation with the optimal thickness of 1 nm is developed and an excellent HfO2/Si0.7Ge0.3 interface with Dit of 1.53 × 1011 eV−1cm−2 @ E−Ev = 0.36 eV is attained. After detailed analysis of the chemical structure of the HfO2/IL/Si-cap/Si0.7Ge0.3 using X-ray photoelectron spectroscopy (XPS), it is confirmed that the excellent HfO2/Si0.7Ge0.3 interface is realized by preventing the formation of Hf-silicate/Hf-germanate and Si oxide originating from the reaction between HfO2 and Si0.7Ge0.3 substrate.

Si0.5Ge0.5 Channel FinFET Preparation on an In Situ Doped SiGe SRB and Its Electrical Characteristics Optimization

“…Its poor SS performance may be related to the high Dit due to the lack of Si 0.5 Ge 0.5 channel passivation, because HfO 2 was directly employed as the high-k gate dielectric. 20 Additionally, combined with the output characteristic of I DS -V DS , its small I ON may be caused by the high S/D series resistance because its contact on the S/ D region was formed directly on the Si 0.5 Ge 0.5 fin without S/D epitaxy or silicide process, 21 and the contact on the S/D region was far from the gate of the device due to limitation of our lithography conditions.…”

Modeling the Initial Stages of Si(100) Thermal Oxidation: An Ab-initio Approach

“…Although SiO 2 is gradually replaced as a gate dielectric by other materials with much higher dielectric constants [2,3] -generally referred to as high-k dielectrics -an ultra-thin SiO 2 passivation layer that is grown on the Si substrate before the deposition of the high-k film substantially improves the device performance [4][5][6] and is therefore typically used. In the course of the ongoing down-scaling trend, research interest recently shifts towards low-temperature chemicalbased bottom-up fabrication approaches [7][8][9] in which the production of ultra-thin SiO 2 layers is of crucial importance. SiO 2 layers are typically fabricated via thermal oxidation of Si.…”