Investigating the Shielding Effect of Pulse Transformer Operation in Isolated Gate Drivers for SiC MOSFETs

Abstract

Wide-bandgap technology evolution compels the advancement of efficient pulse-width gate-driver devices. Integrated enhanced gate-driver planar transformers are a source of electromagnetic disturbances due to inter-winding capacitances, which serve as a route to common-mode(CM) currents. This paper will simulate, via ANSYS Q3D Extractor, the unforeseen parasitic effects of a pulse planar transformer integrated in a SiC MOSFET gate-driver card. Moreover, the pulse transformer will be ameliorated by adding distinctive shielding layers aiming to suppress CM noise effects and endure high dv/dt occurrences intending to validate experimental tests. The correlation between stray capacitance and dv/dt immunity results after shielding insertion will be reported.

Equivalent Circuit Model of a Pulse Planar Transformer and Endurance to Abrupt dv/dt

“…Q3D Extractor exploits the Finite Element Method (FEM) and method of moments to provoke an electromagnetic field solution. It relies on the simplification of Maxwell's equations, termed quasistatic approximation by anticipating that the size of the analyzed design is diminutive compared to the wavelength of maximum sought frequency where the coupling between magnetic and electric fields can be ignored [18]. As depicted in Fig.…”

“…2. Common mode current path in electrically isolated gate drivers in half bridge (HB) configuration [9] In high power applications, opto-isolator technologies are rarely used given their parasitic capacitance and the difficulties for integration of optical fibers commands. Recent gate drivers mainly use two technologies: Digital isolators and pulse transformers.…”