Wide-bandgap technology evolution compels the advancement of efficient pulse-width gate-driver devices. Integrated enhanced gate-driver planar transformers are a source of electromagnetic disturbances due to inter-winding capacitances, which serve as a route to common-mode(CM) currents. This paper will simulate, via ANSYS Q3D Extractor, the unforeseen parasitic effects of a pulse planar transformer integrated in a SiC MOSFET gate-driver card. Moreover, the pulse transformer will be ameliorated by adding distinctive shielding layers aiming to suppress CM noise effects and endure high dv/dt occurrences intending to validate experimental tests. The correlation between stray capacitance and dv/dt immunity results after shielding insertion will be reported.

Wide band gap (WBG) semiconductor materials offer faster and more reliable power electronic components in electric energy conversion systems. However, their faster switching speed and abilities to operate at higher frequency than silicium devices have brought new challenges such as Electromagnetic interference (EMI) issues. In gate driver applications, EMI issues must be tackled given the close proximity between gate driver systems and WBG power modules. This paper focuses on planar pulse transformers for gate drivers in high power applications (3,3kV, 500A SiC module). This study tries to give a standard procedure to design then simulate pulse transformers with their electrostatic shielding. First, a design guideline using Altium Designer is proposed to respect European standards. A method to extract the transformer design from Altium to Ansys is also proposed. Finally, a frequency analysis is discussed to use in Ansys simulations and parameters extraction. Tests have been performed to check the proposed transformers EMC immunity under a 125 kV µs −1 common mode transient immunity (CMTI) test.