Investigation and a practical compact network model of thermal stress in integrated circuits

Abstract

This paper first investigates the non-uniform spatial thermal distribution in sub-100nm integrated circuits. A practical network-based Compact Thermal Modeling (CTM) technique has been proposed to model this thermal stress. The proposed technique, which can be integrated with modern CAD tools, represents IC package as a network in which a set of boundary nodes serve as surrogates for physical regions of the chip. In this network a junction node represents the chip's power junction, and arcs permit thermal communication between adjacent nodes. Due to the complex nature of micro-and nano-systems, the discrete models (resulting from the finite element method (FEM) or other methods) are usually very large (of the order of 100,000). Even though modern computers are able to handle engineering problems of this size, the system-level simulation would become prohibitive if the detailed models were directly used. The proposed CTM is condensed using Static Matrix Condensation methodology where the system matrices obtained by the spatial discretization of heat transfer partial differential equation (PDE) are reduced by the elimination of heat sources, surface nodes and internal nodes, however maintaining the thermal communication among the nodes. The formal conversion of governing PDE systems to low-dimensional ordinary differential equation (ODE) systems is to reduce the complexity, and at the same time preserve the accuracy of the model. The reduced system can be used to either synthesize a resistive network or formulate a set of connection equations to be connected to higher simulation levels.

A review for compact model of graphene field-effect transistors

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