Investigation and Localization of the SiGe Source/Drain (S/D) Strain-Induced Defects in PMOSFET With 45-nm CMOS Technology

Cheng, Ching-Yuan; Fang, Yean–Kuen; Hsieh, J.C.; Hsia, H.; Sheu, Yae‐Lin; Lu, Wen-Tai; Chen, W.M.; Lin, Shieh-Shing

doi:10.1109/led.2007.895446

Cited by 35 publications

(19 citation statements)

References 15 publications

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“…87 Such a possibility is analogous to the well-known phenomenon of stresses induced in a transistor which has SiGe source and drain regions. 88 However, during ion irradiation, the ␣-Si is subject to viscous flow [89][90][91] which could presumably allow for accommodation of the volumetric expansion and minimal resulting substrate stresses in patterned material. Thus, the possibility of stresses in the crystalline phase existing as a result of the amorphization process in patterned material needs further investigation but for purposes of clarity has not been addressed here.…”

Section: ͑10͒mentioning

confidence: 99%

Stressed multidirectional solid-phase epitaxial growth of Si

Rudawski

Jones

Morarka

et al. 2009

Journal of Applied Physics

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The study of the solid-phase epitaxial growth ͑SPEG͒ process of Si ͑variously referred to as solid-phase epitaxy, solid-phase epitaxial regrowth, solid-phase epitaxial crystallization, and solid-phase epitaxial recrystallization͒ amorphized via ion implantation has been a topic of fundamental and technological importance for several decades. Overwhelmingly, SPEG has been studied ͑and viewed͒ as a single-directional process where an advancing growth front between amorphous and crystalline Si phases only has one specific crystallographic orientation. However, as it pertains to device processing, SPEG must actually be considered as multidirectional ͑or patterned͒ rather than bulk in nature with the evolving growth interface having multiple crystallographic orientations. Moreover, due to the increasingly ubiquitous nature of stresses presented during typical Si-based device fabrication, there is great interest in specifically studying the stressed-SPEG process. This work reviews the progress made in understanding the multidirectional SPEG and, more importantly, stressed multidirectional SPEG process. For the work reviewed herein, ͑001͒ Si wafers with ͗110͘-aligned, intrinsically stressed Si 3 N 4 / SiO 2 patterning consisting of square and line structures were used with unmasked regions of the Si substrate amorphized via ion implantation. It is revealed that the stresses generated in the Si substrate from the patterning, both in line and square structures, alter the kinetics and geometry of the multidirectional SPEG process and can influence the formation of mask-edge defects which form during growth to different degrees as per differences in the substrate stresses generated by each type of patterning. Likewise, it is shown that application of external stress from wafer bending during SPEG in specimens with and without patterning can also influence the geometry of the evolving growth interface. Finally, the effect of the addition of SPEG-enhancing impurities during multidirectional stressed growth is observed to alter the evolution of the growth interface, thus suggesting that stress influences on growth are much less than those from dopants. Within the context of prior work, attempts are made to correlate the prior observations in single-directional stressed SPEG with the observations from patterned stressed SPEG reviewed herein. However, as is argued in this review, it ultimately appears that much of the research performed on understanding the single-directional stressed-SPEG process cannot be reasonably extended to the multidirectional stressed-SPEG process.

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Section: ͑10͒mentioning

confidence: 99%

Stressed multidirectional solid-phase epitaxial growth of Si

Rudawski

Jones

Morarka

et al. 2009

Journal of Applied Physics

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“…First, as compared with control device, the reduced LS VG level of the embedded SiGe S/D device implies the reduction of or . However, previous literature had reported that SiGe S/D process may lead higher [20,21]. In other words, it can only be assumed that the reduced mainly contributed to the decreased LS VG of SiGe S/D device.…”

Section: Resultsmentioning

confidence: 93%

Investigation of Low‐Frequency Noise Characterization of 28‐nm High‐k pMOSFET with Embedded SiGe Source/Drain

Tsai

Chen

et al. 2014

Journal of Nanomaterials

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We have studied the low-frequency noise characterizations in 28-nm high-k (HK) pMOSFET with embedded SiGe source/drain (S/D) through 1/ noise and random telegraph noise measurements simultaneously. It is found that uniaxial compressive strain really existed in HK pMOSFET with embedded SiGe S/D. The compressive strain induced the decrease in the tunneling attenuation length reflecting in the oxide trap depth from Si/SiO 2 interface to the HK layer, so that the oxide traps at a distance from insulator/semiconductor interface cannot capture carrier in the channel. Consequently, lower 1/ noise level in HK pMOSFET with embedded SiGe S/D is observed, thanks to the less carrier fluctuations from trapping/detrapping behaviors. This result represents an intrinsic benefit of HK pMOSFET using embedded SiGe S/D in low-frequency noise characteristics.

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“…Generally, epitaxial SiGe layer, where atomically Ge contents induce the film-strain, has been suggested for the sub-0.1 μm high speed and low-power CMOS [3]. Although the epitaxial SiGe is believed to be "compatible" to the processing of Si wafer based CMOS, it is hard to be realize in the large-scaled flat-panel display applications because the SiGe has to be fabricated in polycrystalline texture, which demonstrates a different complexion on the electric performance, not epitaxial film [4].…”

Section: Introductionmentioning

confidence: 99%

Compressive Stressed P-Channel Polycrystalline-Silicon Thin-Film Transistors for High Field-Effect Mobility

Park

Seok

Kim

et al. 2015

IEEE Electron Device Lett.

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A compressively stressed polycrystalline-silicon (poly-Si) TFT was successfully demonstrated on a tensile stressed glass substrate. The layer of a-Si:H/bare glass was annealed for 45 hrs with a sharp annealing and slow cooled condition in order to form compressive strain on the a-Si:H film. Then, the a-Si:H was crystallized by NiSi 2 seed-induced lateral crystallization having (110) preferred texture and the top-gated TFT was fabricated. The electrical properties were excellent comparing with the strain-free poly-Si TFT and especially the field-effect mobility increased 9.3 times higher.Index Terms-Strain silicon, polycrystalline-silicon thin-film transistor (poly-Si TFT), compressive stress.

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Investigation and Localization of the SiGe Source/Drain (S/D) Strain-Induced Defects in PMOSFET With 45-nm CMOS Technology

Cited by 35 publications

References 15 publications

Stressed multidirectional solid-phase epitaxial growth of Si

Stressed multidirectional solid-phase epitaxial growth of Si

Investigation of Low‐Frequency Noise Characterization of 28‐nm High‐k pMOSFET with Embedded SiGe Source/Drain

Compressive Stressed P-Channel Polycrystalline-Silicon Thin-Film Transistors for High Field-Effect Mobility

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