Investigation of analog/RF performance of staggered heterojunctions based nanowire tunneling field-effect transistors

Chakraborty, Avik; Sarkar, Angsuman

doi:10.1016/j.spmi.2015.01.005

Cited by 21 publications

(12 citation statements)

References 45 publications

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“…A lower TGF indicates reduced input device ability and higher power dissipation. 23 Figure 5 clearly shows that a lower TGF is obtained with a device of shorter gate length. Figure 6 demonstrates the variation of output resistance (R out ) with respect to gate-to-source voltage (V GS ) for different channel lengths.…”

Section: Impact Of Gate-length Downscaling On Analog Performance Paramentioning

confidence: 94%

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Radio frequency/analog and linearity performance of a junctionless double gate metal–oxide–semiconductor field-effect transistor

Baral¹,

Biswal²,

et al. 2017

SIMULATION

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The analog/radio frequency (RF) and linearity performance of a junctionless double gate metal-oxide-semiconductor field-effect transistor (JL DGMOS) is investigated using the numerical TCAD device simulator. JL DGMOSs have shown great promise for high-performance digital applications due to their superior short channel effect performance and ease of fabrication. In analog and RF circuit applications, linearity testing and RF performance is a major issue that is encountered due to non-linear behavior of the devices. Therefore, in this paper, different RF/analog and linearity performance figures of merits such as transconductance, intrinsic gain, the transconductance generation factor, the cut off frequency, the maximum frequency of oscillation, the gain bandwidth product, the variable intercept point of second order, the variable intercept point of third order, inter modulation distortion, the third-order intercept point, and 1-dB compression have been presented. Moreover, the effect of gate-length downscaling on these performance parameters has been carried out. The results indicate that the down scaled JL DGMOS shows great promise to become a competitive contender for analog/mixed signal system on chip applications by demonstrating a significant improvement in its RF performance with gate-length downscaling.

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Section: Impact Of Gate-length Downscaling On Analog Performance Paramentioning

confidence: 94%

“…A lower TGF indicates reduced input device ability and higher power dissipation. 23 Figure 5 clearly shows that a lower TGF is obtained with a device of shorter gate length.…”

Section: Impact Of Gate-length Downscaling On Analog Performance Pmentioning

confidence: 94%

Radio frequency/analog and linearity performance of a junctionless double gate metal–oxide–semiconductor field-effect transistor

Baral¹,

Biswal²,

et al. 2017

SIMULATION

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show abstract

“…In the simulation, driftediffusion transport model is included neglecting impact ionization. Lombardi mobility (Constant Voltage and Temperature, CVT) model is used to capture mobility degradation due to parallel and perpendicular field and temperature dependency [22]. CONMOB model also considered for low field mobility related to doping density [23,24].…”

Section: Device Structures Its Parameters and Operationmentioning

confidence: 99%

Performance investigation of InAs based dual electrode tunnel FET on the analog/RF platform

Anand

Sarin

2016

Superlattices and Microstructures

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“…Consequently, the DMGE-HJLTFET provides superior metrics in terms of logic and analog/RF performance as compared with conventional a HJLTFET, that is to say, it can generate higher ON-state current, higher transconductance, higher output transconductance and higher f T and GBW. Therefore, it will have great potential in future ultra-low power and high frequency integrated circuit applications [33][34][35][36][37].…”

Section: Introductionmentioning

confidence: 99%

Design and Investigation of a Dual Material Gate Arsenic Alloy Heterostructure Junctionless TFET with a Lightly Doped Source

et al. 2019

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This paper designs and investigates a novel structure of dual material gate-engineered heterostructure junctionless tunnel field-effect transistor (DMGE-HJLTFET) with a lightly doped source. Similar to the conventional HJLTFET, the proposed structure still adopts an InAs/GaAs0.1Sb0.9 heterojunction at source and channel interface and employs a polarization electric field at the arsenic heterojunction induced by the lattice mismatch in the InAs and GaAs0.1Sb0.9 zinc blende crystal to improve band to band tunneling (BTBT) current. However, the gate electrode is divided into three parts in DMGE-HJLTFET namely the auxiliary gate (M1), control gate (M2) and tunnel gate (M3) with workfunctions ΦM1, ΦM2 and ΦM3, where ΦM1 = ΦM3 < ΦM2, which not only improves ON-state current but also decreases the OFF-state current. In addition, a lightly doped source is used to further decrease the OFF-state current of this device. Simulation results indicate that DMGE-HJLTFET provides superior metrics in terms of logic and analog/radio frequency (RF) performance as compared with conventional HJLTFET, the maximum ON-state current and transconductance of the DMGE-HJLTFET increases up to 5.46 × 10−4 A/μm and 1.51 × 10−3 S/μm at 1.0 V drain-to-source voltage (Vds). Moreover, average subthreshold swing (SSave) of DMGE-HJLTFET is as low as 15.4 mV/Dec at low drain voltages. Also, DMGE-HJLTFET could achieve a maximum cut-off frequency (fT) of 423 GHz at 0.92 V gate-to-source voltage (Vgs) and a maximum gain bandwidth (GBW) of 82 GHz at Vgs = 0.88 V, respectively. Therefore, it has great potential in future ultra-low power integrated circuit applications.

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Investigation of analog/RF performance of staggered heterojunctions based nanowire tunneling field-effect transistors

Cited by 21 publications

References 45 publications

Radio frequency/analog and linearity performance of a junctionless double gate metal–oxide–semiconductor field-effect transistor

Radio frequency/analog and linearity performance of a junctionless double gate metal–oxide–semiconductor field-effect transistor

Performance investigation of InAs based dual electrode tunnel FET on the analog/RF platform

Design and Investigation of a Dual Material Gate Arsenic Alloy Heterostructure Junctionless TFET with a Lightly Doped Source

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