Investigation of buffer traps in AlGaN/GaN-on-Si devices by thermally stimulated current spectroscopy and back-gating measurement

Abstract

Thermally stimulated current (TSC) spectroscopy and high-voltage back-gating measurement are utilized to study GaN buffer traps specific to AlGaN/GaN lateral heterojunction structures grown on a low-resistivity Si substrate. Three dominating deep-level traps in GaN buffer with activation energies of ΔET1 ∼ 0.54 eV, ΔET2 ∼ 0.65 eV, and ΔET3 ∼ 0.75 eV are extracted from TSC spectroscopy in a vertical GaN-on-Si structure. High back-gate bias applied to the Si substrate could influence the drain current in an AlGaN/GaN-on-Si high-electron-mobility transistor in a way that cannot be explained with a simple field-effect model. By correlating the trap states identified in TSC with the back-gating measurement results, it is proposed that the ionization/deionization of both donor and acceptor traps are responsible for the generation of buffer space charges, which impose additional modulation to the 2DEG channel.

Improved modeling of GaN HEMTs for predicting thermal and trapping-induced-kink effects

“…The surface trapping, which is related to polarization-induced surface states, can be reduced by proper surface passivation [4]. However, the buffer trapping cannot be ignored, especially for GaN on Si substrate [5]. The stronger lattice mismatch between GaN and Si results in free ions that behave as electron traps [6].…”

Crosstalk in monolithic GaN-on-Silicon power electronic devices

“…The influence on the device characteristics has been primarily attributed to reduction in 2DEG carrier density as the conducting substrate acts as a second gate and could change the potential distribution across the 2DEG at the AlGaN-GaN interface in the device structure. Ionization/deionization of both donor and acceptor traps responsible for the generation of buffer space charges, has also attributed to additional modulation of the 2DEG channel [11].…”

Lateral Charge Transport in the Carbon-Doped Buffer in AlGaN/GaN-on-Si HEMTs

“…Fig. 1(c) shows the lumped-element representation of the device structure including the primary vertical leakage paths and capacitances normally used to interpret substrate bias experiments assuming 1D conduction [11,[13][14][15][16][17][18][19]. Only negative substrate bias, VSUB, is considered here since this corresponds to the polarity experienced under the drain in a transistor under OFF state conditions.…”

“…Thus, it is necessary to understand the charge storage and transport in the various layers of the buffer to predict the long term stability of these devices. Substrate bias experiments provide an excellent tool to study charge trapping and transport in the buffer and effectively distinguish surface and bulk induced current collapse [14][15][16]. Monitoring the substrate bias dependence of the channel conductivity, and its dispersion as the ramp-rate and temperature are varied, allowed a model for the transport within each layer within the buffer to be constructed [13,[17][18][19].…”