Investigation of Cycling-Induced Dummy Cell Disturbance in 3D NAND Flash Memory

Zou, Xingqi; Jin, Lei; Jiang, Dandan; Chen, Guoxing; Huo, Zongliang

doi:10.1109/led.2017.2785843

Cited by 18 publications

(10 citation statements)

References 11 publications

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“…In charge trapping layer, the drift-diffusion model and charge trapping/de-trapping model are taken into account. Meanwhile, non-local tunneling (NLT) model through tunneling layer and blocking layer is considered [2]. The interaction between free carriers and trapped carriers is governed by carrier capture phenomenon calculated by Shockley-Read-Hall (SRH) theory and carrier emission contributed by thermal and Poole-Frenkel effect [4].…”

Section: Device and Experimentsmentioning

confidence: 99%

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Impact of Cycling Induced Intercell Trapped Charge on Retention Charge Loss in 3-D NAND Flash Memory

Jia

Lü

Zhang

et al. 2020

IEEE J. Electron Devices Soc.

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As the 3D NAND technology developing toward more and more stack layers, it is essential to shrink the gate length (Lg) and inter-gate space (Ls). However, one of key concerns of scaling Lg/Ls 3D NAND flash is post-cycling data retention characteristics. The impact of cycling induced intercell trapped charge on two primary charge loss mechanisms (vertical and lateral charge loss) was studied in this work. According to experimental analysis and TCAD simulation, it is found that, in vertically scaled 3D NAND, the vertical charge loss is deteriorated not only by the cycling induced tunnel oxide degradation (introducing interface/oxide traps), but also by the cycling induced intercell trapped charge (enhancing word-lines edge electric field), on account of the enhanced Poole-Frenkel effect and tunneling effect. On the other hand, the cycling induced intercell trapped charge can also suppress lateral charge migration. Therefore, the vertical charge loss, rather than the lateral charge migration, still can be the dominant factor for post-cycling retention characteristics in scaling Lg/Ls 3D NAND flash memory. INDEX TERMS 3D NAND flash memory, data retention, intercell trapped charge, PE cycling.

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Section: Device and Experimentsmentioning

confidence: 99%

“…For the demand of higher bit density and lower bit cost, three-dimension (3D) NAND flash memory with vertical channel type cells has become the mainstream of nonvolatile memory technology [1], [2]. Triple level cell (TLC) and quad level cell (QLC) technologies will further achieve larger data density [3].…”

Section: Introductionmentioning

confidence: 99%

Impact of Cycling Induced Intercell Trapped Charge on Retention Charge Loss in 3-D NAND Flash Memory

Jia

Lü

Zhang

et al. 2020

IEEE J. Electron Devices Soc.

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“…In our work, the experiment is based on charge trapping 3D vertical channel NAND flash test chips [11]. Fig.…”

Section: Experiments and Simulationmentioning

confidence: 99%

Analysis and Optimization of Threshold Voltage Variability by Polysilicon Grain Size Simulation in 3D NAND Flash Memory

Yang

Xia

Shi

et al. 2020

IEEE J. Electron Devices Soc.

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The impact of linear correlation between lognormal distribution grain size mean and sigma along the polysilicon channel on threshold voltage (V th) variability has been investigated in three dimensional (3D) NAND flash. The variety of grain size mean and sigma results in the unstable V th variability. To obtain a stable V th distribution with various grain size mean, the grain size mean dependent V th variability sensitivity to the grain size sigma was used to optimize the linear correlation between grain size mean and sigma via TCAD simulation. The optimized linear correlation with stable V th variability is obtained except for the "unbalance region" affected by the combination of grain boundaries and positions with these grain size mean and sigma values resulting in the slightly shrinking V th variability. Our results strongly suggest that this approach could guide the direction of polysilicon crystallization optimization to obtain stable V th distribution with the predicted linear correlation between grain size mean and sigma.

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“…Electronics 2020, 9, 268 2 of 7 through WL10) and bottom cells (WL0 through WL4) were divided and the NLSB generated by the WL was analyzed [14][15][16]. Therefore, it is necessary to explain the different potential boosting phenomena occurring at each WL.…”

Section: Structure and Simulationsmentioning

confidence: 99%

“…Previous studies analyzed how the NLSB phenomenon occurs when the bias applied to the selected WL or the pattern of adjacent cells changes [10][11][12][13]. In this study, the top cells (WL11 through WL15), middle cells (WL6 through WL10) and bottom cells (WL0 through WL4) were divided and the NLSB generated by the WL was analyzed [14][15][16]. Therefore, it is necessary to explain the different potential boosting phenomena occurring at each WL.…”

Section: Introductionmentioning

confidence: 99%

Investigation of Inhibited Channel Potential of 3D NAND Flash Memory According to Word-Line Location

et al. 2020

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Natural local self-boosting (NLSB) was analyzed according to the location of a selected word-line (WL) where potential boosting occurs. When the same pattern occurred, it was found that the top cells (WL11 through WL15) and bottom cells (WL0 through WL4) have identically symmetrical potential boosting. In addition, in the region of the middle cells (WL6 through WL10), a slight change in the potential boosting was also almost the same. In the 3D NAND, where there was a dummy WL (DWL), the NLSB for the edge WL changed as the pattern of the DWL changed. The DWL did not affect the NLSB of the main cell, regardless of the pattern. Therefore, the high potential of the edge WL could reduce the potential difference between the main cell and the edge WL using the DWL.

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Investigation of Cycling-Induced Dummy Cell Disturbance in 3D NAND Flash Memory

Cited by 18 publications

References 11 publications

Impact of Cycling Induced Intercell Trapped Charge on Retention Charge Loss in 3-D NAND Flash Memory

Impact of Cycling Induced Intercell Trapped Charge on Retention Charge Loss in 3-D NAND Flash Memory

Analysis and Optimization of Threshold Voltage Variability by Polysilicon Grain Size Simulation in 3D NAND Flash Memory

Investigation of Inhibited Channel Potential of 3D NAND Flash Memory According to Word-Line Location

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