Investigation of Cycling-Induced VT Instabilities in NAND Flash Cells via Compact Modeling

Paolucci, Giovanni M.; Miccoli, Carmine; Compagnoni, Christian Monzio; Crespi, Luciano; Spinelli, A.S.; Lacaita, A.L.

doi:10.1109/imw.2012.6213684

Cited by 2 publications

(3 citation statements)

References 13 publications

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“…This value of activation energy had been also observed in earlier retention experiments [51]. Careful account of additional effects which may compromise a reliable extraction of E A , such as interface-state and mobility recovery [230,231] or disturbs [232], is required. The last data to be discussed relate to the cycling conditions dependence.…”

Section: Charge Detrappingsupporting

confidence: 69%

“…Interface state annealing manifests itself via a reduction of the activation energy, down from the 1.1 eV associated to detrapping to about 0.7 eV [230,231] or even 0.15 eV [249], and are also characterized by a non-uniform distribution over the cell area, usually peaked at the STI edges [74,250]. However, it has been suggested that their effect is dominant for high values of the read current only [230,231], while playing a minor role with respect to charge detrapping as the read current is reduced.…”

Section: Interface State Recoverymentioning

confidence: 99%

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Reliability of NAND Flash Memories: Planar Cells and Emerging Issues in 3D Devices

2017

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Abstract:We review the state-of-the-art in the understanding of planar NAND Flash memory reliability and discuss how the recent move to three-dimensional (3D) devices has affected this field. Particular emphasis is placed on mechanisms developing along the lifetime of the memory array, as opposed to time-zero or technological issues, and the viewpoint is focused on the understanding of the root causes. The impressive amount of published work demonstrates that Flash reliability is a complex yet well-understood field, where nonetheless tighter and tighter constraints are set by device scaling. Three-dimensional NAND have offset the traditional scaling scenario, leading to an improvement in performance and reliability while raising new issues to be dealt with, determined by the newer and more complex cell and array architectures as well as operation modes. A thorough understanding of the complex phenomena involved in the operation and reliability of NAND cells remains vital for the development of future technology nodes.

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Section: Charge Detrappingsupporting

confidence: 69%

Section: Interface State Recoverymentioning

confidence: 99%

Reliability of NAND Flash Memories: Planar Cells and Emerging Issues in 3D Devices

2017

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“…The characterization results evidenced that the phenomenon is unlikely ascribed only to a general V T instability that occurs in presence of stochastic charge trapping/de-trapping events in the tunnel-oxide/interface like for RTN [7], [18], [19] since the fail bits increase is localized in the first group of cells read (see Fig. 5).…”

Section: Discussion On the Tre Naturementioning

confidence: 95%

First Evidence of Temporary Read Errors in TLC 3D-NAND Flash Memories Exiting From an Idle State

Zambelli

Micheloni²,

Scommegna³

et al. 2020

IEEE J. Electron Devices Soc.

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This paper presents a new reliability threat that affects 3D-NAND Flash memories when a read operation is performed exiting from an idle state. In particular, a temporary large increase of the fail bits count is reported for the layers read as first after a sequence of program/verify and a idle retention phase. The phenomenon, hereafter called Temporary Read Errors (TRE), is not due to a permanent change of cell threshold voltage between the program verify and the following read operations, but to its transient instability occurring during the idle phase and the first read operations performed on a block. The experimental analysis has been performed on off-the-shelf gigabit-array products to characterize the dependence on the memory operating conditions. The TRE is found to be strongly dependent on the page read, on the read temperature and on the time delay between the first and the second read after the idle state. To emphasize its negative impact at system-level, we have evaluated the induced performance drop on Solid State Drives architectures. INDEX TERMS 3D-NAND flash, characterization, fail bits, read errors, reliability, solid-state drives (SSD).

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Investigation of Cycling-Induced VT Instabilities in NAND Flash Cells via Compact Modeling

Cited by 2 publications

References 13 publications

Reliability of NAND Flash Memories: Planar Cells and Emerging Issues in 3D Devices

Reliability of NAND Flash Memories: Planar Cells and Emerging Issues in 3D Devices

First Evidence of Temporary Read Errors in TLC 3D-NAND Flash Memories Exiting From an Idle State

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