Investigation of Electrothermal Behaviors of 5-nm Bulk FinFET

Jeon, Jongwook; Jhon, Hee‐Sauk; Kang, Myounggon

doi:10.1109/ted.2017.2766214

Cited by 12 publications

(3 citation statements)

References 16 publications

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“…The impact of NBTI effect on FinFET devices has been simulated using Synopsys Sentaurus TCAD version M-2016.12-SP1. Sentaurus is accurate tool that has been used to investigate reliability in FinFET and planar devices [14]. The 3-D bulk FinFET structure (See Fig.…”

Section: Tcad Finfet Simulation Setupmentioning

confidence: 99%

TCAD analysis and modeling for NBTI mechanism in FinFET transistors

Herrera-Moreno

Garcia-Gervacio

Villacorta-Minaya

et al. 2018

IEICE Electron. Express

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Aging is an important concern in long term reliability of semiconductor devices. In this regard, Bias Temperature Instability (BTI) is considered the major aging mechanism in nanometer regime, particularly in FinFET devices. Therefore, a well understanding of BTI mechanism in FinFET technology is of high interest. In this paper, a three-dimensional TCAD analysis about the impact of negative BTI (NBTI) FinFET technology is presented. In addition, a new NBTI degradation model is proposed for FinFET devices that can be incorporated in Spice which allow to consider aging of a circuit in a design phase. The three-dimensional TCAD analysis is performed using Synopsys Sentaurus tool. Results from the proposed model agree with Sentaurus degradation results.where B is the scaling factor and β is the dispersive shape factor. According to [21] and [19], ¼ 0:25 and B ¼ 1:5. The resulting graphic is shown in Fig. 4.

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Section: Tcad Finfet Simulation Setupmentioning

confidence: 99%

TCAD analysis and modeling for NBTI mechanism in FinFET transistors

Herrera-Moreno

Garcia-Gervacio

Villacorta-Minaya

et al. 2018

IEICE Electron. Express

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“…And it necessitates further clarification of SHEs for scaleddown devices [12][13][14]. Furthermore, Jeon and Kumar et al emphasized the importance of considering the source-drain contact design in self-heating studies [14][15][16]. However, current research on SHEs mostly focuses on the BOX layer, and the study of contacts has not received widespread attention [17].…”

Section: Introductionmentioning

confidence: 99%

The heat dissipation path of self-heating effects for the SOI MOSFET by considering the BOX layer and the TiN barrier layer

Li,

Xu,

et al. 2024

J. Phys. D: Appl. Phys.

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Silicon-on-insulator (SOI) devices are widely utilized in high-performance and high-reliability fields, facing challenges from self-heating effects (SHE). However, the research on heat dissipation path closely related to SHE remains incomplete. This paper initiates an in-depth analysis of thermal effects involving the fine structures within heat dissipation path, using ultrafast pulse I-V measurements combined with thermal simulations. It is found in practical processes that the SHE of scaled-down devices decreased by 40% rather than increase. Research shows the improvement is attributed to the reduction in thickness of buried oxide (BOX) layer between different generations of processes, and the decrease in thermal sensitivity. Based on the two-stage SHE mechanism, the study clarified for the first time that the box layer mainly affects first-stage heat dissipation, and the main timescale of impact is about the first 100ns. In addition, the heat dissipation capability of contact can effectively affect the temperature rise of first-stage SHE. For the first time, we reveal that the TiN barrier layer with low thermal conductivity is the key factor limiting heat dissipation through contact. This study represents the crucial step towards a comprehensive investigation of SHE, offering substantial support for device modeling.

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“…When T A increases, the improvement in electrostatic properties [17] and the degradation in carrier transport [18,19] occur simultaneously, which make it complicated to study the SHE. The energy relaxation time in silicon is 0.8 ps [20] . The electron energy-relaxation-length can be 80 nm when considering the saturation velocity in silicon 10 7 cm/s.…”

Section: Introductionmentioning

confidence: 99%

Impact of ambient temperature on the self-heating effects in FinFETs

Yin

Liu

2018

J. Semicond.

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We use an electro-thermal coupled Monte Carlo simulation framework to investigate the self-heating effect (SHE) in 14 nm bulk nFinFETs with ambient temperature (T A ) from 220 to 400 K. Based on this method, nonlocal heat generation can be achieved. Contact thermal resistances of Si/Metal and Si/SiO 2 are selected to ensure that the source and drain heat dissipation paths are the first two heat dissipation paths. The results are listed below: (i) not all input power (Q input ) turns into heat generation in the device region and some is taken out by the thermal non-equilibrium carriers, owing to the serious non-equilibrium transport; (ii) a higher T A leads to a larger ratio of input power turning into heat generation in the device region at the same operating voltages; (iii) SHE can lead to serious degradation in the carrier transport, which will increase when T A increases; (iv) the current degradation can be 8.9% when V ds = 0.7 V, V gs = 1 V and T A = 400 K; (v) device thermal resistance (R th ) increases with increasing of T A , which is seriously impacted by the non-equilibrium transport. Hence, the impact of T A should be carefully considered when investigating SHE in nanoscale devices.

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Investigation of Electrothermal Behaviors of 5-nm Bulk FinFET

Cited by 12 publications

References 16 publications

TCAD analysis and modeling for NBTI mechanism in FinFET transistors

TCAD analysis and modeling for NBTI mechanism in FinFET transistors

The heat dissipation path of self-heating effects for the SOI MOSFET by considering the BOX layer and the TiN barrier layer

Impact of ambient temperature on the self-heating effects in FinFETs

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