2018
DOI: 10.1088/1674-4926/39/9/094011
|View full text |Cite
|
Sign up to set email alerts
|

Impact of ambient temperature on the self-heating effects in FinFETs

Abstract: We use an electro-thermal coupled Monte Carlo simulation framework to investigate the self-heating effect (SHE) in 14 nm bulk nFinFETs with ambient temperature (T A ) from 220 to 400 K. Based on this method, nonlocal heat generation can be achieved. Contact thermal resistances of Si/Metal and Si/SiO 2 are selected to ensure that the source and drain heat dissipation paths are the first two heat dissipation paths. The results are listed below: (i) not all input power (Q input ) turns into heat generation in the… Show more

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...
2
1
1

Citation Types

0
6
0

Year Published

2019
2019
2025
2025

Publication Types

Select...
7

Relationship

0
7

Authors

Journals

citations
Cited by 10 publications
(6 citation statements)
references
References 40 publications
0
6
0
Order By: Relevance
“…Temperature data is determined by the ratio of a•dV BE , which is proportional to the absolute temperature, and V REF , which refers to the complementary to absolute temperature (CTAT). Here, V REF and dV BE can be generated indirectly though the BGR's outputs, 2-V BE (V BEP and V BEN ), operated and balanced by the ADC's pre-operating modulator; the balance ratio of a•dV BE and V BE represents the final temperature output data, k data [12] :…”
Section: Basic Principles and Sensor Architecturesmentioning
confidence: 99%
See 1 more Smart Citation
“…Temperature data is determined by the ratio of a•dV BE , which is proportional to the absolute temperature, and V REF , which refers to the complementary to absolute temperature (CTAT). Here, V REF and dV BE can be generated indirectly though the BGR's outputs, 2-V BE (V BEP and V BEN ), operated and balanced by the ADC's pre-operating modulator; the balance ratio of a•dV BE and V BE represents the final temperature output data, k data [12] :…”
Section: Basic Principles and Sensor Architecturesmentioning
confidence: 99%
“…In our analog front-end circuit design, proportional current ratio n = 7 is used, resulting in a temperature coefficient of 0.167 mV/°C, and the same size triodes of, 2 μm ×2 μm × 10, are used to generate 2-V BE . The bipolar transistor's forward current gain independence bias structure [12] was selected to match the 'current bias gen' component in Fig. 2, in order that the generated V BE is independent of the current gain.…”
Section: Proposed 4-stage Folded Bias Structurementioning
confidence: 99%
“…The heterogeneous integration of various forms of inorganic materials (which encompasses growing numbers of material types) into one electronic system is based on group III-nitride compound semiconductors [17][18][19][20][21][22][23][24][25][26][27][28] . Examples include the following: on-chip frequency upconversion [29] , nanomechanical optical detection [30,31] , solid-state neutron detection [32][33][34] , piezoelectric resonators and electrical and harmonic generators [35][36][37][38][39][40] , strain-gated transistors (SGTs) [41] , multiple-valued logic (MVL) circuits [42] , single-photon emission [43][44][45] , water splitting [46][47][48][49][50][51] , solar-blind photodetection [52] , pressure [53] , gas [54] , pH [55] , sensors, white light generation from light-emitting diodes (LEDs) [56][57][58] and from laser diodes (LDs) [59] , metal-oxidesemiconductor field-effect transistors (MOSFETs) [60]…”
Section: Introductionmentioning
confidence: 99%
“…The scaling down of the device dimension leads to a few nanometers’ thickness of silicon film above the buried-oxide (BOX) of SOI structure and high power densities, resulting in the dramatic decrease of thermal conductivity of silicon in nanoscale SOI device [4,5,6]. In such a nanoscale SOI device, the aggravated self-heating effect (SHE) is ubiquitous because of the increased heat generation and the reduced thermal diffusion [7,8]. The thermally induced unreliability caused by the SHEs is a pressing issue for advanced UTB SOI MOSFET, which is positively activated in lattice temperature [9,10].…”
Section: Introductionmentioning
confidence: 99%