Investigation of gate oxide short in FinFETs and the test methods for FinFET SRAMs

Abstract

When CMOS technologies enter nanometer scale, FinFET has become one of the most promising devices because of the superior electrical characteristics. Nonetheless, due to the scaling of dielectric thickness and the occurring of line-edge roughness, FinFETs may suffer the gate oxide short. Gate oxide short is a defect that has been widely discussed in planar bulk MOSFETs. But for FinFETs, the defect characteristics have not been studied yet. In this paper, we investigate the fault behaviors of the gate oxide short in FinFETs. The investigation includes both tied-gate and independent-gate FinFETs. Based on the TCAD mixed-mode simulations, we discover that the gate oxide short in the two types of FinFETs causes different fault behaviors from each other. Compared to planar bulk MOSFETs, the fault behaviors are even more complex. In addition to the discussion at device level, we also discuss the corresponding SRAM testing. For detecting gate oxide short in FinFET SRAMs, we propose two new test methods. By using TCAD transient simulations, we prove the two methods' test efficacy of detecting the gate oxide shorts uncovered by traditional test methods. 2013 IEEE 31st VLSI Test Symposium (VTS) 978-1-4673-5543-8/13/$31.00 ©2013 IEEE

Fault Modeling in Controllable Polarity Silicon Nanowire Circuits

“…Moreover, GOS causes a weak inversion and tightens the channel for carriers, leads to a slight increase of V T h (ΔV T h = 170mV ). The negative ID when the VDD = low, which happens in bulk CMOS and FinFET [25,16] , is observed here when the remaining gates of the transistor allow carriers to pass through the channel. For example, for faulty n-type devices used in SP logic gates, polarity controls constantly permit electrons to pass through channel, and therefore negative ID exists when the VD decreases.…”

“…The authors in [12,13] investigated open and short faults on FinFETs, and they showed that Stuck-at Open Faults (SOFs) on the back gate of FinFET have a unique effect on the leakage and delay. In [16], the GOS defect on the Fin-FET dielectric have been studied . The amount of Saturation Drain Current (I D(SAT ) ) vastly increases with GOS at the front gate dielectric.…”

“…For instance, stuck-at [8], delay [9], stuck-open [10], and bridging fault [11] are among the most commonly-used models for CMOS technology. For FinFETs, a few number of studies have been conducted in modeling defects such as floating gates and shorts [12,13], stuck-open/stuck-on [14,15], and Gate Oxide Short (GOS) [16]. These studies revealed the deficiency of current CMOS fault models for detecting defects in FinFET circuits, and necessitated a new fault model for test generation purpose.…”

A defect-oriented test approach using on-Chip current sensors for resistive defects in FinFET SRAMs

“…Lin et al [17] investigated the efficacy of using March Tests as well as I DDQ to detect Gate Oxide Shorts (GOS) in FinFET SRAMs. According to the authors, this type of defects causes more complex fault behaviours in FinFETs than in planar transistors due to their unique structure.…”

“…Using exhaustive March tests to sensitize faults results in expensive manufacturing tests, as the test cost is directly related to the time each product stays on the tester [13]. Disparate approaches, such as monitoring the static or dynamic current consumption of SRAM cells [14][15][16][17], have been proposed to improve the detection of weak defects. Nevertheless, their efficacy regarding FinFET devices affected by resistive defects is unknown.…”