Investigation of Intermittent Resistive Faults in Digital CMOS Circuits

Abstract

No fault found (NFF) is a major threat in extremely dependable high-end process node integrated systems, in e.g., avionics. One category of NFFs is the intermittent resistive fault (IRF), often originating from bad (e.g., via-or TSV-based) interconnections. This paper will show the impact of these faults on the behavior of a digital CMOS circuit via simulation. As the occurrence rate of this kind of defects can take e.g., one month, while the duration of the defect can be as short as 50 ns, thus to evoke and detect these faults is a huge scienti¯c challenge. Two methods to detect short pulses induced by IRFs are proposed. To improve the task of maintenance of avionics and reduce the current high debugging costs, an on-chip data logging system with time stamp and stored environmental conditions is introduced. Finally, a hardware implementation of an IRF generator is presented.

A New Monitor Insertion Algorithm for Intermittent Fault Detection

“…In-situ on-line monitoring is widely used to detect timingfaults [4]- [6] at the chip level. Timing violation along a data path can occur due to process, voltage and temperature variations, aging and IRF [7]. In-situ on-line monitoring techniques can be used for timing-error detection and correction in critical paths [4], timing slack measurements [6], adaptive voltage scaling [8], aging detection [9] and IRF detection as well [3].…”

Detecting intermittent resistive faults in digital CMOS circuits

“…However, none of the previous work has considered the problem of IRFs in detail. We have proposed a model for IRFs and analyzed the influence of IRFs on analogue [8] as well as digital circuits [9] at the transistor level. In [4], we presented an extension of the mixed-signal boundary-scan standard, IEEE 1149.4, to detect IRFs in boards.…”

“…Several examples of measured IRFs have been presented in [17], [9]. Based on this experimental data, we developed a software module to generate these faults in a Cadence Virtuoso environment.…”

“…The model has been implemented in Verilog-A allows replacing a normal wire in the net list by one including an IRF. By using this model, analogue mixed-signal [8] as well as digital circuits [9] can be evaluated at the transistor level. The next sub-section will show some results of IRF simulation and the validation functionality of the proposed IRF detection sensor.…”

Testing for Intermittent Resistive Faults in CMOS Integrated Systems

“…Emulation-based hardware fault injection is an alternative solution for accelerating fault injection. This technique also allows studying the behaviour of a circuit in real time, and also large (PCB-based) systems can then be validated in real-time [13,14].…”