Investigation of Negative DIBL Effect and Miller Effect for Negative Capacitance Nanowire Field-Effect-Transistors

Abstract

In this study, the negative DIBL (N-DIBL), negative differential resistance (NDR), and Miller effect of a negative capacitance nanowire filed-effect-transistor (negative capacitance (NC) NWFET) were analyzed by employing the custom-built SPICE model. In the simulation, the minimum subthreshold swing (SS) reduced to 40 mV/decade with negligible hysteresis, and the on-current amplified by approximately three times. The N-DIBL effect was analyzed by building a model, and the results indicated that the N-DIBL is negatively correlated with the SS. Hence, it is indispensable to make trade-offs between the N-DIBL and SS in NC NWFET applications. Moreover, the Miller effect of a NCFET-based inverter was investigated for the first time. The Miller effect of the NC NWFET-based inverter was considerably improved owing to a high on-current and negative internal gate voltage (when external gate voltage is set to 0V), which is beneficial for high-speed circuit building based on NC NWFETs. The overshoot of the NC NWFET-based inverter is ~43.1% less than that of the NWFET-based inverter, and the propagation delay of the NC NWFET-based inverter is ~73.1% less than that of the NWFET-based inverter at ferroelectric thickness TFE=3nm.

Junction Design and Complementary Capacitance Matching for NCFET CMOS Logic

“…16b inset) for NCFETs with CCM. Although [23] claimed a reduction in Miller Effect for NCFETs, here the opposite is demonstrated. This is rooted in CCM, wherein gate-to-drain capacitance CGD as seen by the input is in parallel with Cinv of the opposing complementary FET, thus increasing the total capacitance which undergoes a Miller effect.…”

“…assessment of polarization switching speed (dP/dt); 2.) AC circuit analysis enabled by either spice model fitting to DC NCFET TCAD or hardware data or self-consistent solving of the Landau-Khalatnikov (L-K) equation with a compact FET model [12], [22][23][24]. Regarding 1.…”

“…Regarding 2. ), compact modeling methodology is simply assumed to equally apply to NCFETs and conventional FETs [12], [22][23][24]; however, such an assumption is potentially risky. Instead, TCAD is used explicitly to simulate the transient behavior of NCFETs, and the results suggest a need for new types of compact models which can accurately capture transient changes in capacitance matching.…”

Performance Upper Limit of Sub-10 nm Monolayer MoS2Transistors with MoS2–Mo Electrodes

“…As shown in Figure , the drain-source currents ( I ds ) decrease down to the off-state under the negative gate voltage, and I ds increases significantly as the V g goes more negative in devices with short channel length. It can be ascribed to the lowered barrier as a result of the short-channel effect. − Specifically, the potential energy barrier for electrons in the channel is lowered as channel length is reduced. As the channel length in the depletion region is reduced, the gate charges are partially contributed by the source and drain, and the controllability of the gate significantly deteriorates.…”

Recent Developments in Negative Capacitance Gate-All-Around Field Effect Transistors: A Review

“…They obtained a minimum SS of 40 mV/dec and three times larger Ion in NC NWGAA-FET. Besides, overshoot and the propagation delay of the NC NWGAA-FET-based inverter were ~43.1 % and ~73.1 % less than those of the NW GAA-FET-based inverter at ferroelectric thickness TFE of 3 nm [104].…”