Investigation of novel attributes of single halo dual-material double gate MOSFETs for analog/RF applications

Mohankumar, N.; Syamal, Binit; Sarkar, Chandan Kumar

doi:10.1016/j.microrel.2009.06.006

Cited by 33 publications

(20 citation statements)

References 19 publications

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“…The key figures of merit which characterize the analog performance of a MOSFET are the output conductance (g d ), transconductance (g m ), intrinsic gain (g m /g d ) and the transconductance generation factor (g m /I D ) of the device [20,21]. Further, the gate capacitance (C G ) which is normally defined as the sum of parasitic gate-to-source (C gs ) and gate-to-drain (C gd ) capacitances plays a vital role in analog circuits.…”

Section: Analog Performancementioning

confidence: 99%

“…The RF performance is mainly characterized by unitygain frequency (F t ), maximum power gain frequency (F max ), short-circuit current gain (A ishort ) and unilateral power gain (U) of a MOSFET [21,22]. The A ishort and U interms of Y-parameters can be expressed as [22,23] …”

Section: Rf Performancementioning

confidence: 99%

“…Here, instead of using approximated F t and F max equations, Y-parameter matrix generated by performing the small-signal ac analysis has been used to get the exact values of F t and F max . The equations used for extracting F t and F max are [21] …”

Section: Rf Performancementioning

confidence: 99%

See 2 more Smart Citations

Impact of Segregation Layer on Scalability and Analog/RF Performance of Nanoscale Schottky Barrier SOI MOSFET

Patil

Qureshi²

2012

JSTS:Journal of Semiconductor Technology and Science

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Abstract-In this paper, the impact of segregation layer density (N DSL ) and length (L DSL ) on scalability and analog/RF performance of dopant-segregated Schottky barrier (DSSB) SOI MOSFET has been investigated in sub-30 nm regime. It has been found that, although by increasing the N DSL the increased off-state leakage, short-channel effects and the parasitic capacitances limits the scalability, the reduced Schottky barrier width at source-to-channel interface improves the analog/RF figures of merit of this device. Moreover, although by reducing the L DSL the increased voltage drop across the underlap length reduces the drive current, the increased effective channel length improves the scalability of this device. Further, the gain-bandwidth product in a commonsource amplifier based on optimized DSSB SOI MOSFET has improved by ~40% over an amplifier based on raised source/drain ultrathin-body SOI MOSFET. Thus, optimizing N DSL and L DSL of DSSB SOI MOSFET makes it a suitable candidate for future nanoscale analog/RF circuits

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Section: Analog Performancementioning

confidence: 99%

Section: Rf Performancementioning

confidence: 99%

See 1 more Smart Citation

Impact of Segregation Layer on Scalability and Analog/RF Performance of Nanoscale Schottky Barrier SOI MOSFET

Patil

Qureshi²

2012

JSTS:Journal of Semiconductor Technology and Science

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show abstract

“…Due to continuous downscaling of CMOS technology and the improved RF figure of merits (FOMs), subthreshold MOSFETs have been adopted in various RF applications such as low power receiver for wireless personal area network (WPAN) [4], low noise amplifier [5] and RF front-end for low power mobile TV [6] etc. Apart from their extremely low power consumption, subthreshold MOSFETs are attractive for system-on-chip (SoC) applications, where the analog/RF circuits can be fabricated with digital circuits in the same integrated circuit by similar process to reduce the cost and improve the performance [7].…”

Section: Introductionmentioning

confidence: 99%

FinFETs using reverse substrate layer with improved gate capacitance characteristics for subthreshold application

Wei

Zhong

Luo

et al. 2015

Solid-State Electronics

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“…The double-gate (DG) MOSFET provide excellent immunity to SCEs, higher drive current and lower leakage current. The presence of second gate increases the effective gate control thereby reducing DIBL [2].…”

mentioning

confidence: 99%

Analysis of Single Halo Double Gate MOSFETs using high-k dielectrics

Nirmal

Kumar

Shruti

et al. 2011

2011 3rd International Conference on Electronics Computer Technology

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Double-gate (DG) MOSFETs came into popularity because of its excellent scalability and better immunity to Short Channel Effects. They are used for CMOS applications beyond the 70 nm node of the SIA roadmaap. However DG devices with channel lengths below 100nm show considerable leakage current and threshold voltage roll off. In this paper, we investigate the influence of channel engineering on the performances of Double Gate (DG) MOSFETs using high-k dielectrics for system-on-chip applications. A Single Halo Double Gate (SH DG) MOSFET is simulated using 2D device simulator and performance is analysed for parameters such as Early voltage, electron velocity and electron mobility. The impact of high-k gate dielectrics on the device short channel performance is studied over a wide range of dielectric permittivity. The device shows 20% increase in drain current as compared to conventional MOSFET. The integration of high-k gate dielectrics further enhances the performance. Drain current increases by 28% and early voltage increases by 34% as the dielectric value increases. The electron velocity also increases with increasing dielectric value.

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Investigation of novel attributes of single halo dual-material double gate MOSFETs for analog/RF applications

Cited by 33 publications

References 19 publications

Impact of Segregation Layer on Scalability and Analog/RF Performance of Nanoscale Schottky Barrier SOI MOSFET

Impact of Segregation Layer on Scalability and Analog/RF Performance of Nanoscale Schottky Barrier SOI MOSFET

FinFETs using reverse substrate layer with improved gate capacitance characteristics for subthreshold application

Analysis of Single Halo Double Gate MOSFETs using high-k dielectrics

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