Investigation of parasitic resistance and capacitance effects in nanoscaled FinFETs and their impact on static random-access memory cells

Huang, Bo-Rong; Meng, Fan-Hsuan; King, Ya‐Chin; Lin, Chrong Jung

doi:10.7567/jjap.56.04cd11

Cited by 9 publications

(5 citation statements)

References 31 publications

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“…Despite these remarkable results, the effect of the Tri-Gate 3D architecture on the switching behavior of lateral AlGaN/GaN based devices has not yet been investigated and there are concerns about the possible capacitance increase due to its 3D nature, as it has been reported for other technologies such as bulk FinFETs [25].…”

Section: Introductionmentioning

confidence: 99%

Fast-Switching Tri-Anode Schottky Barrier Diodes for Monolithically Integrated GaN-on-Si Power Circuits

Nela

Kampitsis

et al. 2020

IEEE Electron Device Lett.

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Tri-Anode GaN Schottky Barrier Diodes (SBDs) have recently shown excellent DC performance with low turn-on voltage and large breakdown thanks to their 3D contact structure around the two-dimensional electron gas (2DEG) channel. However, the 3D nature of the Tri-Anode structure is also often believed to hinder the device switching performance. In this work, we demonstrate that, on the contrary, the Tri-Anode architecture significantly enhances the device switching performance with respect to conventional planar SBDs, as shown by a substantial decrease in the recovery charge and an improvement in frequency response. The Tri-Anode SBDs excellent static and dynamic performance is then applied to a real circuit to demonstrate a monolithically integrated high-frequency Full Bridge Rectifier. These results show the potential of Tri-Anode SBDs for high-efficiency and fast-switching power integrated circuits.

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Section: Introductionmentioning

confidence: 99%

Fast-Switching Tri-Anode Schottky Barrier Diodes for Monolithically Integrated GaN-on-Si Power Circuits

Nela

Kampitsis

et al. 2020

IEEE Electron Device Lett.

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“…Introduction: Fin field-effect transistor (FinFET) has been the mainstream complementary metal-oxide semiconductor (CMOS) logic technology in mass production for power-efficient high-performance system-on-chip applications [1,2]. Although FinFET demonstrates superior short channel performance over conventional planar technology to extend transistor scaling, parasitic capacitance becomes increasingly prominent with aggressive device shrinking at advanced nodes, which subsequently degrades overall device and circuit performance [3,4]. Thus, innovative process integration schemes are demanded to minimise FinFET parasitic capacitance.…”

mentioning

confidence: 99%

Hybrid low‐ k spacer scheme for advanced FinFET technology parasitic capacitance reduction

Wang

et al. 2020

Electron. lett.

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Low-dielectric constant (low-k) material is critical for advanced FinFET technology parasitic capacitance reduction to enable lowpower and high-performance applications. Silicon Oxycarbonnitride (SiOCN) is one of the most promising low-k materials for FinFET gate sidewall spacer. The k value of SiOCN can be controlled in the range of 4.1-5.2 by modifying the chemical contents during the deposition process. However, the integration of SiOCN with k value lower than 5.2 for advanced FinFET technology faces substantial challenges associated with the material damage from subsequent manufacturing processes. Here, the authors demonstrate a hybrid low-k spacer scheme on a fully integrated 7 nm FinFET technology platform, in which SiOCN with k value of 4.5 was successfully integrated along the sidewalls of the gate electrode as spacer while retaining the structural integrity and dielectric properties. Device characterisation on the hybrid low-k spacer scheme (k = 4.5) demonstrated 12/11% reduction in P/NFET overlap capacitance (C OV) and 3% reduction in ring oscillator effective capacitance (C EFF) in comparison to the baseline reference using SiOCN with k value of 5.2 as spacer. Furthermore, reliability characterisation confirmed the dielectric breakdown voltage (V BD) and leakage current (I LKG) of the hybrid low-k spacer (k = 4.5) were comparable to the baseline reference (k = 5.2), meeting the technology requirements.

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“…197 These insulating layers represent parasitic capacitances to the device that are similar in nature to those previously described for the metal interconnect. [198][199][200] Reducing these device level parasitic capacitances has become increasingly important as gate and contact critical dimensions have been scaling slower than contacted gate pitch. 201 This means that parasitic fringe capacitances (such as the contact-to-gate and epi-to-gate, see Fig.…”

Section: Overlooked Dielectrics and Low-k Everywhere!mentioning

confidence: 99%

“…6a) are becoming increasingly more significant. 198 Similarly, parasitic capacitances associated with the shallow trench isolation (STI) are also becoming increasingly important (see Fig. 6b).…”

Section: Overlooked Dielectrics and Low-k Everywhere!mentioning

confidence: 99%

Review—Beyond the Highs and Lows: A Perspective on the Future of Dielectrics Research for Nanoelectronic Devices

Jenkins

Austin

Conley

et al. 2019

ECS J. Solid State Sci. Technol.

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High-dielectric constant (high-k) gate oxides and low-dielectric constant (low-k) interlayer dielectrics (ILD) have dominated the nanoelectronic materials research scene over the past two decades, but they have recently reached a state of maturity and perhaps the limits of their scaling. Based on this, there is a need for a systematic review summarizing not only the historic research and achievements on high-k and low-k dielectrics, but also emerging device applications as well as an outlook of future challenges. We begin by first reviewing the factors that drove the emergence of low-k and high-k materials in nanoelectronics as ILD and gate dielectric materials, respectively, and the challenges and limits these materials ultimately approached in terms of permittivity scaling. We then illustrate that gate dielectric and ILD applications represent just a small fraction of the numerous dielectrics utilized in present day nanoelectronic products where permittivity scaling is now being increasingly demanded for materials such as dielectric spacers, trench isolation, and etch stopping layers. We conclude by examining the numerous new applications for dielectric materials that are emerging as the semiconductor industry transitions to novel patterning schemes, prepares for life post CMOS scaling, and explores ways to natively embed device functionality in the metal interconnect. For the former, we specifically examine the “colorful” requirements for the various enabling dielectric hardmask and spacer materials utilized in pitch division-multi-pattern processes and then discuss the role that selective area deposition of dielectrics and metals could play in reducing the complexity of such patterning processes. For the latter, we review the use of both high-k and low-k dielectrics in various metal-insulator-metal (MIM) structures as Fermi level de-pinning layers, tunnel diodes, and back-end-of-line (BEOL) compatible capacitive and resistive switching random access memory (ReRAM) elements. We further examine how dielectrics can hinder or aid new forms of computing such as quantum and neuromorphic in reaching their full potential. In conclusion, we find that while the field of dielectrics has a long history, it remains vibrant with numerous exciting new and old research vectors awaiting further exploration.

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Investigation of parasitic resistance and capacitance effects in nanoscaled FinFETs and their impact on static random-access memory cells

Cited by 9 publications

References 31 publications

Fast-Switching Tri-Anode Schottky Barrier Diodes for Monolithically Integrated GaN-on-Si Power Circuits

Fast-Switching Tri-Anode Schottky Barrier Diodes for Monolithically Integrated GaN-on-Si Power Circuits

Hybrid low‐ k spacer scheme for advanced FinFET technology parasitic capacitance reduction

Review—Beyond the Highs and Lows: A Perspective on the Future of Dielectrics Research for Nanoelectronic Devices

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