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A thorough investigation of the parasitic resistance and capacitance (RC) effects of a single-fin FinFET on logic CMOS devices and circuits is presented. As parasitic RC effects become increasingly prominent in nanoscaled FinFET technologies, they are critical to the overall device and circuit performance. In addition, the effects of dummy patterns as well as multifin structures are analyzed and modeled in detailed. By incorporating parasitic resistance and capacitance extracted by both measurement and simulation, the static and dynamic performance characteristics of standard six transistor static random-access memory (6T-SRAM) cells are comprehensively evaluated as an example of parasitic RC effects in this investigation.

A thorough analysis of the FinFET resistance and current distribution is presented. By combining multiple conventional and novel measurement techniques, the key components that contribute to the parasitic resistance of FinFETs can be quantified. Through a three-dimensional (3D) FinFET resistance network model, the impact of the FinFET 3D structure on the current distribution and parasitic resistance is analyzed. The heterogeneous current distribution, known as the current crowding effect, is also discussed with possible alleviation methods through 3D simulation.