2018
DOI: 10.1109/ted.2017.2786143
|View full text |Cite
|
Sign up to set email alerts
|

Investigation of Porous Silicon-Based Edge Termination for Planar-Type TRIAC

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...
1
1
1

Citation Types

0
3
0

Year Published

2018
2018
2022
2022

Publication Types

Select...
2
1

Relationship

0
3

Authors

Journals

citations
Cited by 3 publications
(3 citation statements)
references
References 18 publications
0
3
0
Order By: Relevance
“…The relevance of PSi implementation was validated for low-pass filters (9). The same masking layer was also successfully used during the etching of PSi TRIAC peripheries (see last part) (7). In spite of an efficient PSi localization, the lossy bulk silicon wafer under the PSi layer is known to degrade the device performances in the case of RF passive elements.…”
Section: New Challenges In Rf Devices Integrating Psimentioning
confidence: 99%
See 2 more Smart Citations
“…The relevance of PSi implementation was validated for low-pass filters (9). The same masking layer was also successfully used during the etching of PSi TRIAC peripheries (see last part) (7). In spite of an efficient PSi localization, the lossy bulk silicon wafer under the PSi layer is known to degrade the device performances in the case of RF passive elements.…”
Section: New Challenges In Rf Devices Integrating Psimentioning
confidence: 99%
“…The remaining issue is to find a way to further increase blocking voltages. For this purpose, an improved edge structure with PS layers on both sides of the p-well is currently under investigation (7).…”
Section: Psi For Ac Power Switches (Triac) Peripheriesmentioning
confidence: 99%
See 1 more Smart Citation