Investigation of Self-Heating Effects in Vacuum Gate Dielectric Gate-all-Around Vertically Stacked Silicon Nanowire Field Effect Transistors

Su, Yali; Lai, Junhua; Sun, Lanxiang

doi:10.1109/ted.2020.3017452

Cited by 15 publications

(9 citation statements)

References 43 publications

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“…Three uniform verticallystacked GAA Si NSs channels are observed and thickness (width) of the NSs is about 9 nm (25.6nm), implying the good control of the integration thermal budget and well-controlled Si NSs release processes with high GeSi selective etch ratio to Si. 33,34 The corresponding EDX maps for Si, Ge, Hf, O, Ti, Al, C and W distributions are shown in Fig. 2j.…”

Section: Resultsmentioning

confidence: 99%

Improving Driving Current with High-Efficiency Landing Pads Technique for Reduced Parasitic Resistance in Gate-All-Around Si Nanosheet Devices

Tian

Zhang

et al. 2022

ECS J. Solid State Sci. Technol.

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In order to improve the driving ability of vertically-stacked gate-all-around (GAA) Si nanosheets (NSs) devices, a high-efficiency hybrid pattern technique with the SiNx spacer-image transfer and conventional photolithography pattern was proposed and implemented to form size-enlarged landing pads (LPs) on nanometer-scale fins at the same time, which increase the volumes of electrical conductance pathway between NS channel and source and drain (SD) electrodes with high process efficiency and compatibility with traditional mass production technology. Due to introduced new structures, the parasitic resistance of the devices is reduced by 99.8% compared with those w./o. LPs. Therefore, ~3 times and ~2 times driving current enhancements for 500 nm gate length n-type and p-type MOSFETs are obtained, respectively. The results indicate the proposed GAA NS FET fabrication process with LPs by high-efficiency hybrid pattern technique a promising solution for improving the device driving ability for stacked GAA Si NSs devices in future.

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Section: Resultsmentioning

confidence: 99%

Improving Driving Current with High-Efficiency Landing Pads Technique for Reduced Parasitic Resistance in Gate-All-Around Si Nanosheet Devices

Tian

Zhang

et al. 2022

ECS J. Solid State Sci. Technol.

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“…During the fabrication of stacked GAA Si NW/NS MOSFETs, a multi-step high temperature annealing process is needed, such as shallow trench isolation (STI) annealing and source drain (SD) activation. The high temperature processes would result in a fast atom diffusion in multi-layer GeSi/Si stacks, and the abrupt interfaces among the multi-layer GeSi/Si stacks layers would be destroyed, which would affect the structure, morphology, and quality of the formed Si NS channels [ 19 , 20 , 21 ]. In order to study the influence of annealing temperature on the GeSi selective etch, the samples with GeSi/Si stack arrays were annealed at 650 °C, 700 °C, 750 °C, 800 °C, 850 °C, and 900 °C for 30 s, respectively, in N 2 atmosphere using rapid thermal annealing (RTA) equipment.…”

Section: Resultsmentioning

confidence: 99%

Optimization of Structure and Electrical Characteristics for Four-Layer Vertically-Stacked Horizontal Gate-All-Around Si Nanosheets Devices

Zhang

et al. 2021

Nanomaterials

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In this paper, the optimizations of vertically-stacked horizontal gate-all-around (GAA) Si nanosheet (NS) transistors on bulk Si substrate are systemically investigated. The release process of NS channels was firstly optimized to achieve uniform device structures. An over 100:1 selective wet-etch ratio of GeSi to Si layer was achieved for GeSi/Si stacks samples with different GeSi thickness (5 nm, 10 nm, and 20 nm) or annealing temperatures (≤900 °C). Furthermore, the influence of ground-plane (GP) doping in Si sub-fin region to improve electrical characteristics of devices was carefully investigated by experiment and simulations. The subthreshold characteristics of n-type devices were greatly improved with the increase of GP doping doses. However, the p-type devices initially were improved and then deteriorated with the increase of GP doping doses, and they demonstrated the best electrical characteristics with the GP doping concentrations of about 1 × 1018 cm−3, which was also confirmed by technical computer aided design (TCAD) simulation results. Finally, 4 stacked GAA Si NS channels with 6 nm in thickness and 30 nm in width were firstly fabricated on bulk substrate, and the performance of the stacked GAA Si NS devices achieved a larger ION/IOFF ratio (3.15 × 105) and smaller values of Subthreshold swings (SSs) (71.2 (N)/78.7 (P) mV/dec) and drain-induced barrier lowering (DIBLs) (9 (N)/22 (P) mV/V) by the optimization of suppression of parasitic channels and device’s structure.

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“…In-situ nitrogen plasma treatment was employed before the deposition of a 50 nm SiNx passivation layer using PECVD. 15 Figure 1 shows the device schematic for the L Top = 500 nm (short Y-gate device), 760 nm (medium Y-gate device), and 960 nm (large Y-gate device) with L Bottom = 200 nm Y-gate HEMTs. The Transmission Electron Microscope (TEM) image of L Top = 960 nm and L Bottom = 200 nm bottom gate Y-gate device is shown in Fig.…”

Section: Methodsmentioning

confidence: 99%

“…Hot carrier effects often cause the device and circuit failure. [11][12][13][14][15][16][17][18] In this paper, as traps stem from HCI, the effect of HCI on the performance for HCI stress time from 0 s to 6000 s was investigated for reliability. Furthermore, Y-shaped gate GaN HEMT with a L top of 500 nm, 760 nm, and 960 nm is compared for a more complete study.…”

mentioning

confidence: 99%

Hot Carrier Injection (HCI) Reliability of Fabricated Y-gate HEMT with Various Top Length

Chen¹,

Yeh²,

Chen³

et al. 2023

ECS J. Solid State Sci. Technol.

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Device degradation due to hot carrier injection (HCI) in different Y-gate HEMT devices is thoroughly analyzed. To further understand the HCI reliability of the Y-gate HEMT devices, the device is fabricated with AlGaN/GaN structure with different top lengths (Ltop). An HCI stress time of 6000 seconds was conducted on these devices, while Vt stability in other stress time domains, leakage current, and transconductance degradation are also discussed. We have demonstrated that increasing the LTop length could avoid the virtual gate effect and disperse the influence of the electric field under HCI stress. Furthermore, the effects of trapping in various locations, such as in the bulk SiN or AlGaN/GaN interface has been discussed. These trapping effects caused by the HCI stress might be the source of the Vth shift. Overall, The large Y-gate HEMT showed the lowest degradation of DC characteristics after the long HCI stress test.

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Investigation of Self-Heating Effects in Vacuum Gate Dielectric Gate-all-Around Vertically Stacked Silicon Nanowire Field Effect Transistors

Cited by 15 publications

References 43 publications

Improving Driving Current with High-Efficiency Landing Pads Technique for Reduced Parasitic Resistance in Gate-All-Around Si Nanosheet Devices

Improving Driving Current with High-Efficiency Landing Pads Technique for Reduced Parasitic Resistance in Gate-All-Around Si Nanosheet Devices

Optimization of Structure and Electrical Characteristics for Four-Layer Vertically-Stacked Horizontal Gate-All-Around Si Nanosheets Devices

Hot Carrier Injection (HCI) Reliability of Fabricated Y-gate HEMT with Various Top Length

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